View LSI53C875A_1233709.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? s14047 LSI53C875A pci to ultra scsi controller technical manual december 2000 version 2.0
ii this document contains proprietary information of lsi logic corporation. the information contained herein is not to be used by or disclosed to third parties without the express written permission of an officer of lsi logic corporation. lsi logic products are not intended for use in life-support appliances, devices, or systems. use of any lsi logic product in such applications without written consent of the appropriate lsi logic officer is prohibited. document db14-000143-01, second edition (december 2000). this document describes the lsi logic LSI53C875A pci to ultra scsi controller and will remain the official reference source for all revisions/releases of this product until rescinded by an update. to receive product literature, visit us at http://www.lsilogic.com. lsi logic corporation reserves the right to make changes to any products herein at any time without notice. lsi logic does not assume any responsibility or liability arising out of the application or use of any product described herein, except as expressly agreed to in writing by lsi logic; nor does the purchase or use of a product from lsi logic convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of lsi logic or third parties. ultra scsi is the term used by the scsi trade association (sta) to describe fast-20 scsi, as documented in the scsi-3 fast-20 parallel interface standard, x3,277-199x. copyright ? 2000 by lsi logic corporation. all rights reserved. trademark acknowledgment the lsi logic logo design, tolerant, and scripts are registered trademarks or trademarks of lsi logic corporation. all other brand and product names may be trademarks of their respective companies. hh
preface iii preface this book is the primary reference and technical manual for the LSI53C875A pci to ultra scsi controller. it contains a complete functional description for the product and also includes complete physical and electrical specifications. audience this manual provides reference information on the LSI53C875A pci to ultra scsi controller. it is intended for system designers and programmers who are using this device to design an ultra scsi port for pci-based personal computers, workstations, servers or embedded applications. organization this document has the following chapters and appendixes: ? chapter 1, general description includes general information about the LSI53C875A. ? chapter 2, functional description describes the main functional areas of the chip in more detail, including interfaces to the scsi bus and external memory. ? chapter 3, signal descriptions contains pin diagrams and signal descriptions. ? chapter 4, registers describes each bit in the operating registers, and is organized by register address. ? chapter 5, scsi scripts instruction set defines all of the scsi scripts instructions that are supported by the LSI53C875A.
iv preface ? chapter 6, electrical specifications contains the electrical characteristics and ac timing diagrams. ? appendix a, register summary is a register summary. ? appendix b, external memory interface diagram examples contains several example interface drawings for connecting the LSI53C875A to external roms. related publications for background information, please contact: ansi 11 west 42nd street new york, ny 10036 (212) 642-4900 ask for document number x3.131-199x (scsi-2) global engineering documents 15 inverness way east englewood, co 80112 (800) 854-7179 or (303) 397-7956 (outside u.s.) fax (303) 397-2740 ask for document number x3.131-1994 (scsi-2); x3.253 ( scsi-3 parallel interface ) endl publications 14426 black walnut court saratoga, ca 95070 (408) 867-6642 document names: scsi bench reference, scsi encyclopedia, scsi tutor prentice hall 113 sylvan avenue englewood cliffs, nj 07632 (800) 947-7700 ask for document number isbn 0-13-796855-8, scsi: understanding the small computer system interface lsi logic world wide web home page www.lsilogic.com
preface v pci special interest group 2575 n.e. katherine hillsboro, or 97214 (800) 433-5177; (503) 693-6232 (international); fax (503) 693-8344 conventions used in this manual the word assert means to drive a signal true or active. the word deassert means to drive a signal false or inactive. hexadecimal numbers are indicated by the prefix ?0x? ?for example, 0x32cf. binary numbers are indicated by the prefix ?0b? ?for example, 0b0011.0010.1100.1111. revision record revision date remarks preliminary 5/00 preliminary draft version of the manual. 1.0 6/00 preliminary version of the manual. 2.0 12/00 final version of the manual.
vi preface
contents vii contents chapter 1 general description 1.1 new features in the LSI53C875A 1-3 1.2 benefits of ultra scsi 1-3 1.3 tolerant ? te c h n o l o gy 1 - 4 1.4 LSI53C875A benefits summary 1-4 1.4.1 scsi performance 1-5 1.4.2 pci performance 1-6 1.4.3 integration 1-6 1.4.4 ease of use 1-6 1.4.5 flexibility 1-7 1.4.6 reliability 1-8 1.4.7 testability 1-8 chapter 2 functional description 2.1 pci functional description 2-2 2.1.1 pci addressing 2-2 2.1.2 pci bus commands and functions supported 2-3 2.1.3 pci cache mode 2-9 2.2 scsi functional description 2-16 2.2.1 scripts processor 2-17 2.2.2 internal scripts ram 2-18 2.2.3 64-bit addressing in scripts 2-19 2.2.4 hardware control of scsi activity led 2-19 2.2.5 designing an ultra scsi system 2-20 2.2.6 prefetching scripts instructions 2-21 2.2.7 opcode fetch burst capability 2-22 2.2.8 load and store instructions 2-22 2.2.9 jtag boundary scan testing 2-23 2.2.10 scsi loopback mode 2-23
viii contents 2.2.11 parity options 2-24 2.2.12 dma fifo 2-27 2.2.13 scsi bus interface 2-32 2.2.14 select/reselect during selection/reselection 2-33 2.2.15 synchronous operation 2-34 2.2.16 interrupt handling 2-37 2.2.17 chained block moves 2-44 2.3 parallel rom interface 2-48 2.4 serial eeprom interface 2-50 2.4.1 default download mode 2-50 2.4.2 no download mode 2-51 2.5 power management 2-51 2.5.1 power state d0 2-52 2.5.2 power state d1 2-52 2.5.3 power state d2 2-53 2.5.4 power state d3 2-53 chapter 3 signal descriptions 3.1 LSI53C875A functional signal grouping 3-2 3.2 signal descriptions 3-3 3.2.1 internal pull-ups on LSI53C875A signals 3-3 3.3 pci bus interface signals 3-4 3.3.1 system signals 3-4 3.3.2 address and data signals 3-5 3.3.3 interface control signals 3-6 3.3.4 arbitration signals 3-7 3.3.5 error reporting signals 3-7 3.3.6 interrupt signal 3-8 3.4 scsi bus interface signals 3-8 3.4.1 scsi bus interface signal 3-8 3.4.2 scsi signals 3-9 3.4.3 scsi control signals 3-9 3.5 gpio signals 3-10 3.6 rom flash and memory interface signals 3-11 3.7 test interface signals 3-12 3.8 power and ground signals 3-13 3.9 mad bus programming 3-14
contents ix chapter 4 registers 4.1 pci configuration registers 4-1 4.2 scsi registers 4-18 4.3 64-bit scripts selectors 4-99 4.4 phase mismatch jump registers 4-103 chapter 5 scsi scripts instruction set 5.1 low level register interface mode 5-1 5.2 high level scsi scripts mode 5-2 5.2.1 sample operation 5-3 5.3 block move instruction 5-6 5.3.1 first dword 5-6 5.3.2 second dword 5-13 5.4 i/o instruction 5-13 5.4.1 first dword 5-14 5.4.2 second dword 5-21 5.5 read/write instructions 5-22 5.5.1 first dword 5-22 5.5.2 second dword 5-23 5.5.3 read-modify-write cycles 5-23 5.5.4 move to/from sfbr cycles 5-24 5.6 transfer control instructions 5-25 5.6.1 first dword 5-26 5.6.2 second dword 5-32 5.7 memory move instructions 5-32 5.7.1 first dword 5-33 5.7.2 read/write system memory from scripts 5-34 5.7.3 second dword 5-34 5.7.4 third dword 5-35 5.8 load and store instructions 5-35 5.8.1 first dword 5-36 5.8.2 second dword 5-37 chapter 6 electrical specifications 6.1 dc characteristics 6-1 6.2 tolerant technology electrical characteristics 6-5
xcontents 6.3 ac characteristics 6-9 6.4 pci and external memory interface timing diagrams 6-11 6.4.1 target timing 6-13 6.4.2 initiator timing 6-19 6.4.3 external memory timing 6-35 6.5 scsi timing diagrams 6-52 6.6 package diagrams 6-58 appendix a register summary appendix b external memory interface diagram examples index customer feedback figures 1.1 typical LSI53C875A system application 1-2 1.2 typical LSI53C875A board application 1-2 2.1 LSI53C875A block diagram 2-2 2.2 parity checking/generation 2-27 2.3 dma fifo sections 2-28 2.4 LSI53C875A host interface scsi data paths 2-29 2.5 regulated termination for ultra scsi 2-33 2.6 determining the synchronous transfer rate 2-35 2.7 block move and chained block move instructions 2-45 3.1 LSI53C875A functional signal grouping 3-2 5.1 scripts overview 5-5 6.1 rise and fall time test condition 6-7 6.2 scsi input filtering 6-7 6.3 hysteresis of scsi receivers 6-7 6.4 input current as a function of input voltage 6-8 6.5 output current as a function of output voltage 6-8 6.6 external clock 6-9 6.7 reset input 6-10 6.8 interrupt output 6-11
contents xi 6.9 pci configuration register read 6-13 6.10 pci configuration register write 6-14 6.11 32-bit operating register/scripts ram read 6-15 6.12 64-bit address operating register/scripts ram read 6-16 6.13 32-bit operating register/scripts ram write 6-17 6.14 64-bit address operating register/scripts ram write 6-18 6.15 nonburst opcode fetch, 32-bit address and data 6-20 6.16 burst opcode fetch, 32-bit address and data 6-22 6.17 back-to-back read, 32-bit address and data 6-24 6.18 back-to-back write, 32-bit address and data 6-26 6.19 burst read, 32-bit address and data 6-28 6.20 burst read, 64-bit address and data 6-30 6.21 burst write, 32-bit address and data 6-32 6.22 burst write, 64-bit address and 32-bit data 6-34 6.23 external memory read 6-36 6.24 external memory write 6-40 6.25 normal/fast memory ( 128 kbytes) single byte access read cycle 6-42 6.26 normal/fast memory ( 128 kbytes) single byte access write cycle 6-43 6.27 normal/fast memory ( 128 kbytes) multiple byte access read cycle 6-44 6.28 normal/fast memory ( 128 kbytes) multiple byte access write cycle 6-46 6.29 slow memory ( 128 kbytes) read cycle 6-48 6.30 slow memory ( 128 kbytes) write cycle 6-49 6.31 64 kbytes rom read cycle 6-50 6.32 64 kbyte rom write cycle 6-51 6.33 initiator asynchronous send 6-52 6.34 initiator asynchronous receive 6-53 6.35 target asynchronous send 6-54 6.36 target asynchronous receive 6-55 6.37 initiator and target synchronous transfer 6-57 6.38 LSI53C875A 160-pin pqfp mechanical drawing 6-58 6.39 169-pin bga mechanical drawing 6-61 b.1 16kbyteinterfacewith200nsmemory b-1 b.2 64kbyteinterfacewith150nsmemory b-2
xii contents b.3 128 kbytes, 256 kbytes, 512 kbytes, or 1 mbyte interface with 150 ns memory b-3 b.4 512 kbyte interface with 150 ns memory b-4 tables 2.1 pci bus commands and encoding types for the LSI53C875A 2-4 2.2 pci cache mode alignment 2-12 2.3 bits used for parity control and generation 2-25 2.4 scsi parity control 2-26 2.5 scsi parity errors and interrupts 2-26 2.6 parallel rom support 2-49 2.7 mode a serial eeprom data format 2-51 2.8 power states 2-52 3.1 LSI53C875A internal pull-ups 3-3 3.2 system signals 3-4 3.3 address and data signals 3-5 3.4 interface control signals 3-6 3.5 arbitration signals 3-7 3.6 error reporting signals 3-7 3.7 interrupt signal 3-8 3.8 scsi bus interface signal 3-8 3.9 scsi signals 3-9 3.10 scsi control signals 3-9 3.11 gpio signals 3-10 3.12 rom flash and memory interface signals 3-11 3.13 test interface signals 3-12 3.14 power and ground signals 3-13 3.15 decode of mad pins 3-14 4.1 pci configuration register map 4-2 4.2 scsi register address map 4-19 4.3 examples of synchronous transfer periods and rates for scsi-1 4-32 4.4 example transfer periods and rates for fast scsi-2 and ultra scsi 4-33 4.5 maximum synchronous offset 4-34 4.6 scsi synchronous data fifo word count 4-44 5.1 scripts instructions 5-3
contents xiii 5.2 scsi information transfer phase 5-12 5.3 read/write instructions 5-24 5.4 transfer control instructions 5-26 5.5 scsi phase comparisons 5-29 6.1 absolute maximum stress ratings 6-2 6.2 operating conditions 6-2 6.3 input capacitance 6-2 6.4 bidirectional signals?mad[7:0], mas/[1:0], mce/, moe/, mwe/ 6-3 6.5 bidirectional signals?gpio0_fetch/, gpio1_master/, gpio[2:4] 6-3 6.6 bidirectional signals?ad[31:0], c_be[3:0]/, frame/, irdy/, trdy/, devsel/, stop/, perr/, par 6-4 6.7 input signals?clk, gnt/, idsel, rst/, sclk, tck, tdi, test_hsc, test_rst, tms, trst/ 6-4 6.8 output signal?tdo 6-4 6.9 output signals?irq/, mac/_testout, req/ 6-5 6.10 output signal?serr/ 6-5 6.11 tolerant technology electrical characteristics for se scsi signals 6-6 6.12 external clock 6-9 6.13 reset input 6-10 6.14 interrupt output 6-10 6.15 pci configuration register read 6-13 6.16 pci configuration register write 6-14 6.17 32-bit operating register/scripts ram read 6-15 6.18 64-bit address operating register/scripts ram read 6-16 6.19 32-bit operating register/scripts ram write 6-17 6.20 64-bit address operating register/scripts ram write 6-18 6.21 nonburst opcode fetch, 32-bit address and data 6-19 6.22 burst opcode fetch, 32-bit address and data 6-21 6.23 back-to-back read, 32-bit address and data 6-23 6.24 back-to-back write, 32-bit address and data 6-25 6.25 burst read, 32-bit address and data 6-27 6.26 burst read, 64-bit address and data 6-29 6.27 burst write, 32-bit address and data 6-31 6.28 burst write, 64-bit address and 32-bit data 6-33 6.29 external memory read 6-35
xiv contents 6.30 external memory write 6-38 6.31 normal/fast memory ( 128 kbytes) single byte access read cycle 6-42 6.32 normal/fast memory ( 128 kbytes) single byte access write cycle 6-43 6.33 slow memory ( 128 kbytes) read cycle 6-48 6.34 slow memory ( 128 kbytes) write cycle 6-49 6.35 = 64 kbytes rom read cycle 6-50 6.36 64 kbyte rom write cycle 6-51 6.37 initiator asynchronous send 6-52 6.38 initiator asynchronous receive 6-53 6.39 target asynchronous send 6-54 6.40 target asynchronous receive 6-55 6.41 scsi-1 transfers (5.0 mbytes) 6-55 6.42 scsi-2 fast transfers 10.0 mbytes (8-bit transfers) or 20.0 mbytes (16-bit transfers) 40 mhz clock 6-56 6.43 ultra scsi transfers 20.0 mbytes (8-bit transfers) or 40.0 mbytes (16-bit transfers) quadrupled 40 mhz clock 6-56 6.44 160 pqfp pin list by location 6-60 6.45 169 bga pin list by location 6-62 a.1 LSI53C875A pci register map a-1 a.2 LSI53C875A scsi register map a-2
LSI53C875A pci to ultra scsi controller 1-1 chapter 1 general description chapter 1 is divided into the following sections: ? section 1.1, ?new features in the LSI53C875A? ? section 1.2, ?benefits of ultra scsi? ? section 1.3, ?tolerant ? technology? ? section 1.4, ?LSI53C875A benefits summary? the LSI53C875A pci to ultra scsi controller brings ultra scsi performance to host adapter, workstation, and general computer designs, making it easy to add a high-performance scsi bus to any pci system. it supports ultra scsi transfer rates with single-ended (se) signaling for scsi devices. the LSI53C875A has a local memory bus for local storage of the device?s bios rom in flash memory or standard eeproms. the LSI53C875A supports programming of local flash memory for updates to bios. chapter 6, ?electrical specifications,? has the chip package and bga specifications. appendix b, ?external memory interface diagram examples,? has system diagrams showing the connections of the LSI53C875A with an external rom or flash memory. the LSI53C875A integrates a high-performance scsi core, a 64-bit pci bus master dma core, and the lsi logic scsi scripts? processor to meet the flexibility requirements of scsi-3 and ultra scsi standards. it implements multithreaded i/o algorithms with a minimum of processor intervention, solving the protocol overhead problems of previous intelligent and nonintelligent adapter designs. figure 1.1 illustrates a typical LSI53C875A system and figure 1.2 illustrates a typical LSI53C875A board application.
1-2 general description figure 1.1 typical LSI53C875A system application figure 1.2 typical LSI53C875A board application pci bus interface controller LSI53C875A pcitowideultra scsi controller pci graphic accelerator pci fast ethernet memory controller memory fixed disk, optical disk printer, tape, and other peripherals central processing unit (cpu) pci bus processor bus ty p i c a l p c i computer system architecture scsi bus 68 pin scsi wide connector LSI53C875A 32 bit pci to scsi controller memory control block flash eeprom serial eeprom pci interface pci address, data, parity and control signals scsi data, parity and control signals memory address/data bus gpio[1:0]
new features in the LSI53C875A 1-3 1.1 new features in the LSI53C875A the LSI53C875A is a drop-in replacement for the lsi53c875 pci to ultra scsi controller, with these additional benefits: ? supports 32-bit pci interface with 64-bit addressing. ? handles scsi phase mismatches in scripts without interrupting the cpu. ? supports jtag boundary scanning. ? supports pc99 power management. ? automatically downloads subsystem vendor id, subsystem id, and pci power management levels d0, d1, d2, and d3. ? improves pci bus efficiency through improved pci caching design. ? transfers load/store data to or from 4 kbytes of internal scripts ram. additional features of the LSI53C875A include: ? hardware control of scsi activity led. ? 32-bit istat registers ( interrupt status zero (istat0) , interrupt status one (istat1) , mailbox zero (mbox0) , mailbox one (mbox1) ). ? optional 944 byte dma fifo supports large block transfers at ultra scsi speeds. the default fifo size of 112 bytes is also supported. 1.2 benefits of ultra scsi ultra scsi is an extension of the spi-2 draft standard that allows faster synchronous scsi transfer rates. when enabled, ultra scsi performs 20 megatransfers per second. the LSI53C875A can perform 16-bit, ultra scsi synchronous transfers as fast as 40 mbytes/s. this advantage is most noticeable in heavily loaded systems or with applications with large block requirements, such as video on-demand and image processing. an advantage of ultra scsi is that it significantly improves scsi bandwidth while preserving existing hardware and software investments. the primary software changes required enable the chip to perform
1-4 general description synchronous negotiations for ultra scsi rates and to enable the clock quadrupler. chapter 2, ?functional description,? contains more information on ultra scsi design. 1.3 tolerant ? technology the LSI53C875A features tolerant technology, which includes active negation on the scsi drivers and input signal filtering on the scsi receivers. active negation actively drives the scsi request, acknowledge, data, and parity signals high rather than allowing them to be passively pulled up by terminators. active negation is enabled by setting bit 7 in the scsi test three (stest3) register. tolerant receiver technology improves data integrity in unreliable cabling environments where other devices would be subject to data corruption. tolerant receivers filter the scsi bus signals to eliminate unwanted transitions, without the long signal delay associated with rc-type input filters. this improved driver and receiver technology helps eliminate double clocking of data, the single biggest reliability issue with scsi operations. the benefits of tolerant technology include increased immunity to noise when the signal is going high, better performance due to balanced duty cycles, and improved fast scsi transfer rates. in addition, tolerant scsi devices do not cause glitches on the scsi bus at power-up or power-down, so other devices on the bus are also protected from data corruption. tolerant technology is compatible with both the alternative one and alternative two termination schemes proposed by the american national standards institute. 1.4 LSI53C875A benefits summary this section of the chapter provides an overview of the LSI53C875A features and benefits. it contains these topics: ? scsi performance ? pci performance ? integration
LSI53C875A benefits summary 1-5 ? ease of use ? flexibility ? reliability ? testability 1.4.1 scsi performance to improve scsi performance, the LSI53C875A: ? has integrated se transceivers. ? bursts up to 512 bytes across the pci bus through its 944 byte fifo. ? performs wide, ultra scsi synchronous transfers as fast as 40 mbytes/s. ? can handle phase mismatches in scripts without interrupting the system processor, eliminating the need for cpu intervention during an i/o disconnect/reselect sequence. ? achieve ultra scsi transfer rates with an input frequency of 20 mhz with the on-chip scsi clock quadrupler. ? includes 4 kbytes internal ram for scripts instruction storage. ? has 31 levels of scsi synchronous offset. ? supports variable block size and scatter/gather data transfers. ? performs sustained memory-to-memory dma transfers to approximately 100 mbytes/s. ? minimizes scsi i/o start latency. ? performs complex bus sequences without interrupts, including restoring data pointers. ? reduces isr overhead through a unique interrupt status reporting method. ? uses load/store scripts instructions which increase performance of data transfers to and from the chip registers without using pci cycles. ? has scripts support for 64-bit addressing. ? supports multithreaded i/o algorithms in scsi scripts with fast i/o context switching.
1-6 general description ? supports additional arithmetic capability with the expanded register move instruction. 1.4.2 pci performance to improve pci performance, the LSI53C875A: ? complies with pci 2.2 specification. ? supports 32-bit 33 mhz pci interface with 64-bit addressing. ? supports dual address cycles which can be generated for all scripts for > 4 gbyte addressability. ? bursts 2, 4, 8, 16, 32, 64, or 128 dword transfers across the pci bus. ? supports 32-bit word data bursts with variable burst lengths. ? prefetches up to 8 dwords of scripts instructions. ? bursts scripts opcode fetches across the pci bus. ? performs zero wait-state bus master data bursts faster than 110 mbytes/s (@ 33 mhz). ? supports pci cache line size register. ? supports pci write and invalidate, read line, and read multiple commands. ? complies with pci bus power management specification rev 1.1. 1.4.3 integration features of the LSI53C875A which ease integration include: ? high-performance scsi core. ? integrated se transceivers. ? full 32-bit pci dma bus master. ? integrated scripts processor. ? memory-to-memory move instructions allow use as a third party pci bus dma controller. 1.4.4 ease of use the LSI53C875A provides:
LSI53C875A benefits summary 1-7 ? up to one megabyte of add-in memory support for bios and scripts storage. ? reduced scsi development effort. ? compiler-compatible with existing lsi53c7xx and lsi53c8xx family scripts. ? direct connection to pci and scsi se. ? development tools and sample scsi scripts available. ? five gpio pins. ? maskable and pollable interrupts. ? wide scsi, a or p cable, and up to 15 devices supported. ? three programmable scsi timers: select/reselect, handshake-to-handshake, and general purpose. the time-out period is programmable from 100 s to greater than 25.6 seconds. ? software for pc-based operating system support. ? support for relative jumps. ? scsi selected as id bits for responding with multiple ids. 1.4.5 flexibility the LSI53C875A provides: ? high level programming interface (scsi scripts). ? ability to program local and bus flash memory. ? selectable 112 or 944 byte dma fifo for backward compatibility. ? tailored scsi sequences execute from main system ram or internal scripts ram. ? flexible programming interface to tune i/o performance or to adapt to unique scsi devices. ? support for changes in the logical i/o interface definition. ? low level access to all registers and all scsi bus signals. ? fetch, master, and memory access control pins. ? separate scsi and system clocks.
1-8 general description ? scsi clock quadrupler bits enable ultra scsi transfer rates with a 20 or 40 mhz scsi clock input. ? selectable irq pin disable bit. ? ability to route system clock to scsi clock. ? compatible with 3.3 v and 5 v pci. 1.4.6 reliability enhanced reliability features of the LSI53C875A include: ? 2 kv esd protection on scsi signals. ? protection against bus reflections due to impedance mismatches. ? controlled bus assertion times (reduces rfi, improves reliability, and eases fcc certification). ? latch-up protection greater than 150 ma. ? voltage feed-through protection (minimum leakage current through scsi pads). ? high proportion (> 25%) of device pins are power or ground. ? power and ground isolation of i/o pads and internal chip logic. ? tolerant technology, which provides: ? active negation of scsi data, parity, request, and acknowledge signals for improved fast scsi transfer rates. ? input signal filtering on scsi receivers improves data integrity, even in noisy cabling environments. 1.4.7 testability the LSI53C875A provides improved testability through: ? access to all scsi signals through programmed i/o. ? scsi loopback diagnostics. ? scsi bus signal continuity checking. ? support for single step mode operation. ? jtag boundary scan.
LSI53C875A pci to ultra scsi controller 2-1 chapter 2 functional description chapter 2 is divided into the following sections: ? section 2.1, ?pci functional description? ? section 2.2, ?scsi functional description? ? section 2.3, ?parallel rom interface? ? section 2.4, ?serial eeprom interface? ? section 2.5, ?power management? the LSI53C875A pci to ultra scsi controller is composed of the following modules: ? 32-bit pci interface with 64-bit addressing ? pci-to-wide ultra scsi controller ? rom/flash memory controller ? serial eeprom controller figure 2.1 illustrates the relationship between these modules.
2-2 functional description figure 2.1 LSI53C875A block diagram 2.1 pci functional description the LSI53C875A implements a pci-to-wide ultra scsi controller. 2.1.1 pci addressing there are three physical pci-defined address spaces: ? pci configuration space. ? i/o space for operating registers. ? memory space for operating registers. 32 bit pci interface, pci configuration register 4kbyte scripts ram 8 dword scripts prefetch buffer 944 byte dma fifo scsi scripts processor operating registers rom/flash serial eeprom local memory bus scsi fifo and scsi control block se tolerant drivers and receivers jtag pci bus jtag bus wide ultra scsi bus rom/flash memory bus 2-wire serial eeprom bus wide ultra scsi controller controller and autoconfiguration memory control
pci functional description 2-3 2.1.1.1 configuration space the host processor uses the pci configuration space to initialize the LSI53C875A through a defined set of configuration space registers. the configuration registers are accessible only by system bios during pci configuration cycles. the configuration space is a contiguous 256 x 8-bit set of addresses. decoding c_be[3:0]/ determines if a pci cycle is intended to access the configuration register space. the idsel bus signal is a ?chip select? that allows access to the configuration register space only. a configuration read/write cycle without idsel is ignored. the eight lower order address bits, ad[7:0], select a specific 8-bit register. ad[10:8] are decoded as well, but they must be zero or the LSI53C875A does not respond. according to the pci specification, ad[10:8] are reserved for multifunction devices. at initialization time, each pci device is assigned a base address for i/o and memory accesses. in the case of the LSI53C875A, the upper 24 bits of the address are selected. on every access, the LSI53C875A compares its assigned base addresses with the value on the address/data bus during the pci address phase. if the upper 24 bits match, the access is for the LSI53C875A and the low-order eight bits define the register being accessed. a decode of c_be[3:0]/ determines which registers and what type of access is to be performed. i/o space ? the pci specification defines i/o space as a contiguous 32-bit i/o address that is shared by all system resources, including the LSI53C875A. base address register zero (i/o) determines which 256-byte i/o area this device occupies. memory space ? the pci specification defines memory space as a contiguous 64-bit memory address that is shared by all system resources, including the LSI53C875A. base address register one (memory) determines which 1 kbyte memory area this device occupies. base address register two (scripts ram) determines the 4 kbyte memory area occupied by scripts ram. 2.1.2 pci bus commands and functions supported bus commands indicate to the target the type of transaction the master is requesting. bus commands are encoded on the c_be[3:0]/ lines during the address phase. pci bus commands and encoding types appear in ta b l e 2 . 1 .
2-4 functional description 2.1.2.1 interrupt acknowledge command the LSI53C875A does not respond to this command as a slave and it never generates this command as a master. 2.1.2.2 special cycle command the LSI53C875A does not respond to this command as a slave and it never generates this command as a master. table 2.1 pci bus commands and encoding types for the LSI53C875A c_be[3:0]/ command type supported as master supported as slave 0b0000 interrupt acknowledge no no 0b0001 special cycle no no 0b0010 i/o read yes yes 0b0011 i/o write yes yes 0b0100 reserved n/a n/a 0b0101 reserved n/a n/a 0b0110 memory read yes yes 0b0111 memory write yes yes 0b1000 reserved n/a n/a 0b1001 reserved n/a n/a 0b1010 configuration read no yes 0b1011 configuration write no yes 0b1100 memory read multiple yes 1 1. see the dma mode (dmode) register. yes (defaults to 0b0110) 0b1101 dual address cycle (dac) yes no 0b1110 memory read line yes 1 yes (defaults to 0b0110) 0b1111 memory write and invalidate yes 2 2. see the chip test three (ctest3) register. yes (defaults to 0b0111)
pci functional description 2-5 2.1.2.3 i/o read command the i/o read command reads data from an agent mapped in i/o address space. all 32 address bits are decoded. 2.1.2.4 i/o write command the i/o write command writes data to an agent mapped in i/o address space. all 32 address bits are decoded. 2.1.2.5 reserved command the LSI53C875A does not respond to this command as a slave and it never generates this command as a master. 2.1.2.6 memory read command the memory read command reads data from an agent mapped in the memory address space. the target is free to do an anticipatory read for this command only if it can guarantee that such a read has no side effects. 2.1.2.7 memory write command the memory write command writes data to an agent mapped in the memory address space. when the target returns ?ready,? it assumes responsibility for the coherency (which includes ordering) of the subject data. 2.1.2.8 configuration read command the configuration read command reads the configuration space of each agent. an agent is selected during a configuration access when its idsel signal is asserted and ad[1:0] are 0b00. 2.1.2.9 configuration write command the configuration write command transfers data to the configuration space of each agent. an agent is selected when its idsel signal is asserted and ad[1:0] are 0b00.
2-6 functional description 2.1.2.10 memory read multiple command this command is identical to the memory read command except that it additionally indicates that the master may intend to fetch more than one cache line before disconnecting. the LSI53C875A supports pci memory read multiple functionality and issues memory read multiple commands on the pci bus when the read multiple mode is enabled. this mode is enabled by setting bit 2 (ermp) of the dma mode (dmode) register. if cache mode is enabled, a memory read multiple command is issued on all read cycles, except opcode fetches, when the following conditions are met: ? the clse bit (cache line size enable, bit 7, dma control (dcntl) register) and the ermp bit (enable read multiple, bit 2, dma mode (dmode) register) are set. ? the cachelinesize register for each function contains a legal burst size value (2, 4, 8, 16, 32, or 64) and that value is less than or equal to the dmode burst size. ? the transfer will cross a cache line boundary. when these conditions are met, the chip issues a memory read multiple command instead of a memory read during all pci read cycles. burst size selection ? the read multiple command reads in multiple cache lines of data in a single bus ownership. the number of cache lines to read is a multiple of the cache line size specified in revision 2.2 of the pci specification. the logic selects the largest multiple of the cache line size based on the amount of data to transfer, with the maximum allowable burst size determined from the dma mode (dmode) burst size bits, and the chip test five (ctest5) ,bit2. 2.1.2.11 dual address cycle (dac) command the LSI53C875A performs dacs when 64-bit addressing is required. refer to the pci 2.2 specification. if any of the selector registers contain a nonzero value, a dac is generated. see 64-bit scripts selectors in chapter 4, ?registers,? for additional information. 2.1.2.12 memory read line command this command is identical to the memory read command, except that it additionally indicates that the master intends to fetch a complete cache
pci functional description 2-7 line. this command is intended for use with bulk sequential data transfers where the memory system and the requesting master might gain some performance advantage by reading to a cache line boundary rather than a single memory cycle. the read line function in the LSI53C875A takes advantage of the pci 2.2 specification regarding issuing this command. if the cache mode is disabled, read line commands are not issued. if the cache mode is enabled, a read line command is issued on all read cycles, except nonprefetch opcode fetches, when the following conditions are met: ? the clse (cache line size enable, bit 7, dma control (dcntl) register) and erl (enable read line, bit 3, dma mode (dmode) register) bits are set. ? the cache line size register must contain a legal burst size value in dwords (2, 4, 8, 16, 32, 64, or 128) and that value is less than or equal to the dma mode (dmode) burst size. ? the transfer will cross a dword boundary but not a cache line boundary. when these conditions are met, the chip issues a read line command instead of a memory read during all pci read cycles. otherwise, it issues a normal memory read command. read multiple with read line enabled ? when both the read multiple and read line modes are enabled, the read line command is not issued if the above conditions are met. instead, a read multiple command is issued, even though the conditions for read line are met. if the read multiple mode is enabled and the read line mode is disabled, read multiple commands are issued if the read multiple conditions are met.
2-8 functional description 2.1.2.13 memory write and invalidate command the memory write and invalidate command is identical to the memory write command, except that it additionally guarantees a minimum transfer of one complete cache line; that is to say, the master intends to write all bytes within the addressed cache line in a single pci transaction unless interrupted by the target. this command requires implementation of the pci cache line size register at address 0x0c in pci configuration space. the LSI53C875A enables memory write and invalidate cycles when bit 0 (wrie) in the chip test three (ctest3) register and bit 4 (wie) in the pci command register are set. when the following conditions are met, memory write and invalidate commands are issued: 1. the clse bit (cache line size enable, bit 7, dma control (dcntl) register), wrie bit (write and invalidate enable, bit 0, chip test three (ctest3) register), and pci configuration command register, bit 4 are set. 2. the cache line size register contains a legal burst size value in dwords (2, 4, 8, 16, 32, 64, or 128) and that value is less than or equal to the dma mode (dmode) burst size. 3. the chip has enough bytes in the dma fifo to complete at least one full cache line burst. 4. the chip is aligned to a cache line boundary. when these conditions are met, the LSI53C875A issues a memory write and invalidate command instead of a memory write command during all pci write cycles. multiple cache line transfers ? the memory write and invalidate command can write multiple cache lines of data in a single bus ownership. the chip issues a burst transfer as soon as it reaches a cache line boundary. the size of the transfer is not automatically the cache line size, but rather a multiple of the cache line size specified in revision 2.2 of the pci specification. the logic selects the largest multiple of the cache line size based on the amount of data to transfer, with the maximum allowable burst size determined from the dma mode (dmode) burst size bits, and chip test five (ctest5), bit2.ifmultiple cache line size transfers are not desired, set the dma mode (dmode) burst size to exactly the cache line size and the chip only issues single cache line transfers.
pci functional description 2-9 after each data transfer, the chip re-evaluates the burst size based on the amount of remaining data to transfer and again selects the highest possible multiple of the cache line size, and no larger than the dma mode (dmode) burst size. the most likely scenario of this scheme is that the chip selects the dma mode (dmode) burst size after alignment, and issues bursts of this size. the burst size is, in effect, throttled down toward the end of a long memory move or block move transfer until only the cache line size burst size is left. the chip finishes the transfer with this burst size. latency ? in accordance with the pci specification, the latency timer is ignored when issuing a memory write and invalidate command such that when a latency time-out occurs, the LSI53C875A continues to transfer up to a cache line boundary. at that point, the chip relinquishes the bus, and finishes the transfer at a later time using another bus ownership. if the chip is transferring multiple cache lines it continues to transfer until the next cache boundary is reached. pci target retry ? during a memory write and invalidate transfer, if the target device issues a retry (stop with no trdy/, indicating that no data was transferred), the chip relinquishes the bus and immediately tries to finish the transfer on another bus ownership. the chip issues another memory write and invalidate command on the next ownership, in accordance with the pci specification. pci target disconnect ? during a memory write and invalidate transfer, if the target device issues a disconnect the LSI53C875A relinquishes the bus and immediately tries to finish the transfer on another bus ownership. the chip does not issue another memory write and invalidate command on the next ownership unless the address is aligned. 2.1.3 pci cache mode the LSI53C875A supports the pci specification for an 8-bit cache line size register located in the pci configuration space. the cache line size register provides the ability to sense and react to nonaligned addresses corresponding to cache line boundaries. in conjunction with the cachelinesize register, the pci commands memory read line, memory read multiple, and memory write and invalidate are each
2-10 functional description software enabled or disabled to allow the user full flexibility in using these commands. 2.1.3.1 enabling cache mode in order to enable the cache logic to issue pci cache commands (memory read line, memory read multiple, and memory write and invalidate) on any given pci master operation the following conditions must be met: ? the cache line size enable bit in the dma control (dcntl) register must be set. ? the pci cachelinesize register must contain a valid binary cache size, i.e. 2, 4, 8, 16, 32, 64, or 128 dwords. only these values are considered valid cache sizes. ? the programmed burst size (in dwords) must be equal to or greater than the cachelinesize register. the dma mode (dmode) register bits [7:6] and chip test five (ctest5) bit 2 are the burst length bits. ? the part must be doing a pci master transfer. the following pci master transactions do not utilize the pci cache logic and thus no pci cache command is issued during these types of cycles: a nonprefetch scripts fetch, a load/store data transfer, or a data flush operation. all other types of pci master transactions will utilize the pci cache logic. the above conditions must be met for the cache logic to control the type of pci cache command that is issued, along with any alignment that may be necessary during write operations. if these conditions are not met for any given pci master transaction, a memory read or memory write is issued and no cache write alignment is done. 2.1.3.2 issuing cache commands in order to issue each type of pci cache command, the corresponding enable bit must be set (2 bits in the case of memory write and invalidate). these bits are detailed below: ? to issue memory read line commands, the read line enable bit in the dma mode (dmode) register must be set.
pci functional description 2-11 ? to issue memory read multiple commands, the read multiple enable bit in the dma mode (dmode) register must be set. ? to issue memory write and invalidate commands, both the write and invalidate enables in the chip test three (ctest3) register and the pci configuration command register must be set. if the corresponding cache command being issued is not enabled then the cache logic falls back to the next command enabled. specifically, if memory read multiple is not enabled and memory read lines are, read lines are issued in place of read multiple. if no cache commands are enabled, cache write alignment still occurs but no cache commands are issued, only memory reads and memory writes. 2.1.3.3 memory read caching the type of memory read command issued depends on the starting location of the transfer and the number of bytes being transferred. during reads, no cache alignment is done (this is not required nor optimal per pci 2.2 specification) and reads will always be either a programmed burst length in size, as set in the dma mode (dmode) and chip test three (ctest3) registers. in the case of a transfer which is smaller than the burst length, all bytes for that transfer are read in one pci burst transaction. if the transfer will cross a dword boundary (a[1:0] = 0b00) a memory read line command is issued. when the transfer will cross a cache boundary (depends on cache line size programmed into the pci configuration register), a memory read multiple command is issued. if a transfer will not cross a dword or cache boundary or if cache mode is not enabled a memory read command is issued. 2.1.3.4 memory write caching writes are aligned in a single burst transfer to get to a cache boundary. at that point, memory write and invalidate commands are issued and continue at the burst length programmed into the dma mode (dmode) register. memory write and invalidate commands are issued as long as the remaining byte count is greater than the memory write and invalidate threshold. when the byte count goes below this threshold, a single memory write burst is issued to complete the transfer. the general pattern for pci writes is: ? a single memory write to align to a cache boundary.
2-12 functional description ? multiple memory write and invalidates. ? a single data residual memory write to complete the transfer. ta b l e 2 . 2 describes pci cache mode alignment. table 2.2 pci cache mode alignment host memory a00h b04h 08h c0ch d10h 14h 18h 1ch e20h 24h 28h 2ch f30h 34h 38h 3ch g40h 44h 48h 4ch h50h 54h 58h 5ch 60h
pci functional description 2-13 2.1.3.5 examples: mr = memory read, mrl = memory read line, mrm = memory read multiple, mw = memory write, mwi = memory write and invalidate. read example 1 ? burst=4dwords,cachelinesize=4dwords: read example 2 ? burst=8dwords,cachelinesize=4dwords: atob: mrl(6bytes) atoc: mrl (13 bytes) atod: mrl (15 bytes) mr (2 bytes) ctod: mrm (5 bytes) ctoe: mrm (15 bytes) mrm (6 bytes) dtof: mrl (15 bytes) mrl (16 bytes) mr (1 byte) atoh: mrl (15 bytes) mrl (16 bytes) mrl (16 bytes) mrl (16 bytes) mrl (16 bytes) mr (2 bytes) atog: mrl (15 bytes) mrl (16 bytes) mrl (16 bytes) mrl (16 bytes) mr (3 bytes) atob: mrl(6bytes) atoc: mrl (13 bytes) atod: mrm (17 bytes) ctod: mrm (5 bytes)
2-14 functional description read example 3 ? burst = 16 dwords, cache line size = 8 dwords: write example 1 ? burst=4dwords,cachelinesize=4dwords: ctoe: mrm (21 bytes) dtof: mrm (31 bytes) mr (1 byte) atoh: mrm (31 bytes) mrm (32 bytes) mrm (18 bytes) atog: mrm (31 bytes) mrm (32 bytes) mr (3 bytes) atob: mrl(6bytes) atoc: mrl (13 bytes) atod: mrl (17 bytes) ctod: mrl(5bytes) ctoe: mrm (21 bytes) dtof: mrm (32 bytes) atoh: mrm (63 bytes) mrl (16 bytes) mrm (2 bytes) atog: 2 transfers, mrm (63 bytes), mr (3 bytes) atob: mw (6 bytes) atoc: mw (13 bytes) atod: mw (17 bytes) ctod: mw (5 bytes) ctoe: mw (3 bytes) mwi (16 bytes) mw (2 bytes)
pci functional description 2-15 write example 2 ? burst=8dwords,cachelinesize=4dwords: dtof: mw (15 bytes) mwi (16 bytes) mw (1 byte) atoh: mw (15 bytes) mwi (16 bytes) mwi (16 bytes) mwi (16 bytes) mwi (16 bytes) mw (2 bytes) atog: mw (15 bytes) mwi (16 bytes) mwi (16 bytes) mwi (16 bytes) mw (3 bytes) atob: mw (6 bytes) atoc: mw (13 bytes) atod: mw (17 bytes) ctod: mw (5 bytes) ctoe: mw (3 bytes) mwi (16 bytes) mw (2 bytes) dtof: mw (15 bytes) mwi (16 bytes) mw (1 byte) atoh: mw (15 bytes) mwi (32 bytes) mwi (32 bytes) mw (2 bytes) atog: mw (15 bytes) mwi (32 bytes) mwi (16 bytes) mw (3 bytes)
2-16 functional description write example 3 ? burst = 16 dwords, cache line size = 8 dwords: 2.1.3.6 memory-to-memory moves memory-to-memory moves also support pci cache commands, as described above, with one limitation. memory write and invalidate on memory-to-memory move writes are only supported if the source and destination address are quad word aligned. if the source and destination are not quad word aligned (that is, source address [2:0] == destination address [2:0]), write aligning is not performed and memory write and invalidate commands are not issued. the LSI53C875A is little endian only. 2.2 scsi functional description the LSI53C875A provides an ultra scsi controller that supports an 8-bit or 16-bit bus. the controller supports wide ultra scsi synchronous transfer rates up to 40 mbytes/s. the scsi core can be programmed with scsi scripts, making it easy to ?fine tune? the system for specific mass storage devices or ultra scsi requirements. the LSI53C875A offers low level register access or a high-level control interface. like first generation scsi devices, the LSI53C875A is atob: mw (6 bytes) atoc: mw (13 bytes) atod: mw (17 bytes) ctod: mw (5 bytes) ctoe: mw (21 bytes) dtof: mw (32 bytes) atoh: mw (15 bytes) mwi (64 bytes) mw (2 bytes) atog: mw (15 bytes) mwi (32 bytes) mw (18 bytes)
scsi functional description 2-17 accessed as a register-oriented device. error recovery and/or diagnostic procedures use the ability to sample and/or assert any signal on the scsi bus. in support of scsi loopback diagnostics, the scsi core may perform a self-selection and operate as both an initiator and a target. the LSI53C875A is controlled by the integrated scripts processor through a high-level logical interface. commands controlling the scsi core are fetched out of the main host memory or local memory. these commands instruct the scsi core to select, reselect, disconnect, wait for a disconnect, transfer information, change bus phases and, in general, implement all aspects of the scsi protocol. the scripts processor is a special high-speed processor optimized for scsi protocol. 2.2.1 scripts processor the scsi scripts processor allows both dma and scsi commands to be fetched from host memory or internal scripts ram. algorithms written in scsi scripts control the actions of the scsi and dma cores. the scripts processor executes complex scsi bus sequences independently of the host = cpu. algorithms may be designed to tune scsi bus performance, to adjust to new bus device types (such as scanners, communication gateways, etc.), or to incorporate changes in the scsi-2 or scsi-3 logical bus definitions without sacrificing i/o performance. scsi scripts are hardware independent, so they can be used interchangeably on any host or cpu system bus. scsi scripts handle conditions like phase mismatch. 2.2.1.1 phase mismatch handling in scripts the LSI53C875A can handle phase mismatches due to drive disconnects without needing to interrupt the processor. the primary goal of this logic is to completely eliminate the need for cpu intervention during an i/o disconnect/reselect sequence. storing the appropriate information to later restart the i/o can be done through scripts, eliminating the need for processor intervention during an i/o disconnect/reselect sequence. calculations are performed such that the appropriate information is available to scripts so that an i/o state can be properly stored for restart later.
2-18 functional description the phase mismatch jump logic powers up disabled and must be enabled by setting the phase mismatch jump enable bit (enpmj, bit 7 in the chip control 0 (ccntl0) register). utilizing the information supplied in the phasemismatchjumpaddress 1(pmjad1) and phase mismatch jump address 2 (pmjad2) registers, described in chapter 4, ?registers,? scripts handles all overhead involved in a disconnect/reselect sequence with a modest number of instructions. 2.2.2 internal scripts ram the LSI53C875A has 4 kbyte (1024 x 32 bits) of internal, general purpose ram. the ram is designed for scripts program storage, but is not limited to this type of information. when the chip fetches scripts instructions or table indirect information from the internal ram, these fetches remain internal to the chip and do not use the pci bus. other types of access to the ram by the chip, except load/store, use the pci bus, as if they were external accesses. the scripts ram powers up enabled by default. the ram can be relocated by the pci system bios anywhere in the 32-bit address space. the base address register two (scripts ram) in the pci configuration space contains the base address of the internal ram. to simplify loading of the scripts instructions, the base address of the ram appears in the scratch register b (scratchb) register when bit 3 of the c h i p te s t tw o ( c t e s t 2 ) register is set. the ram is byte accessible from the pci bus and is visible to any bus mastering device on the bus. external accesses to the ram (by the cpu) follow the same timing sequence as a standard slave register access, except that the required target wait-states drop from 5 to 3. a complete set of development tools is available for writing custom drivers with scsi scripts. for more information on the scsi scripts instructions supported by the LSI53C875A, see chapter 5, ?scsi scripts instruction set.?
scsi functional description 2-19 2.2.3 64-bit addressing in scripts the LSI53C875A has a 32-bit pci interface which provides 64-bit address capability in the initiator mode. dacs can be generated for all scripts operations. there are six selector registers which hold the upper dword of a 64-bit address. all but one of these is static and requires manual loading using a cpu access, a load/store instruction, or a memory move instruction. one of the selector registers is dynamic and is used during 64-bit direct block moves only. all selectors default to zero, meaning the LSI53C875A powers-up in a state where only single address cycles (sacs) are generated. when any of the selector registers are written to a nonzero value, dacs are generated. direct, table indirect and indirect block moves, memory-to-memory moves, load and store instructions, and jumps are all instructions with 64-bit address capability. crossing the 4 gbyte boundary on any one scripts operation is not permitted and software needs to take care that any given scripts operation will not cross the 4 gbyte boundary. 2.2.4 hardware control of scsi activity led the LSI53C875A has the ability to control a led through the gpio_0 pin to indicate that it is connected to the scsi bus. formerly this function was done by a software driver. when bit 5 (led_cntl) in the general purpose pin control zero (gpcntl0) register is set and bit 6 (fetch enable) in the general purpose pin control zero (gpcntl0) register is cleared and the LSI53C875A is not performing an eeprom autodownload, then bit 3 (con) in the interrupt status zero (istat0) register is presented at the gpio_0 pin. the con (connected) bit in interrupt status zero (istat0) is set anytime the LSI53C875A is connected to the scsi bus either as an initiator or a target. this will happen after the LSI53C875A has successfully completed a selection or when it has successfully responded to a selection or reselection. it will also be set when the LSI53C875A wins arbitration in low level mode.
2-20 functional description 2.2.5 designing an ultra scsi system since ultra scsi is based on existing scsi standards, it can use existing driver programs as long as the software is able to negotiate for ultra scsi synchronous transfer rates. additional software modifications are needed to take advantage of the new features in the LSI53C875A. for additional information on ultra scsi, refer to the spi-2 working document which is available from the scsi bbs referenced at the beginning of this manual. chapter 6, ?electrical specifications,? contains ultra scsi timing information. in addition to the guidelines in the draft standard, make the following software and hardware adjustments to accommodate ultra scsi transfers: ? set the ultra enable bit to enable ultra scsi transfers. ? set the tolerant enable bit, bit 7 in the scsi test three (stest3) register, whenever the ultra enable bit is set. ? do not extend the sreq/sack filtering period with s c s i te s t tw o (stest2) bit 1. when the ultra enable bit is set, the filtering period is fixed at 15 ns for ultra scsi, regardless of the value of the sreq/sack filtering bit. ? use the scsi clock quadrupler. a 20 or 40 mhz input must be supplied if using the scsi clock quadrupler for an ultra design. 2.2.5.1 using the scsi clock quadrupler the LSI53C875A can quadruple the frequency of a 20 mhz scsi clock, allowing the system to perform ultra scsi transfers. this option is user selectable with bit settings in the scsi test one (stest1) , scsi test three (stest3) ,and scsi control three (scntl3) registers. at power-on or reset, the quadrupler is disabled and powered down. follow these steps to use the clock quadrupler: step 1. set the sclk quadrupler enable bit ( scsi test one (stest1) ,bit3). step 2. poll bit 5 of the scsi test four (stest4) register. the LSI53C875A sets this bit as soon as it locks in the quadrupled frequency. the frequency lockup takes approximately 100 s.
scsi functional description 2-21 step3. haltthescsiclockbysettingthehaltscsiclockbit( scsi test three (stest3) ,bit5). step 4. set the clock conversion factor using the scf and ccf fields in the scsi control three (scntl3) register. step 5. set the sclk quadrupler select bit ( scsi test one (stest1) , bit 2). step 6. clear the halt scsi clock bit. 2.2.6 prefetching scripts instructions when enabled by setting the prefetch enable bit (bit 5) in the dma control (dcntl) register, the prefetch logic in the LSI53C875A fetches 8 dwords of instructions. the prefetch logic automatically determines the maximum burst size that it can perform, based on the burst length as determined by the values in the dma mode (dmode) register. if the unit cannot perform bursts of at least four dwords, it disables itself. while the chip is prefetching scripts instructions, it will use pci cache commands memory read line, and memory read multiple, if pci caching is enabled. note: this feature is only useful if fetching scripts instructions from main memory. due to the short access time of scripts ram, prefetching is not necessary when fetching instructions from this memory. the LSI53C875A may flush the contents of the prefetch unit under certain conditions, listed below, to ensure that the chip always operates from the most current version of the scripts instruction. when one of these conditions apply, the contents of the prefetch unit are automatically flushed. ? on every memory move instruction. the memory move instruction is often used to place modified code directly into memory. to make sure that the chip executes all recent modifications, the prefetch unit flushes its contents and loads the modified code every time an instruction is issued. to avoid inadvertently flushing the prefetch unit contents, use the no flush option for all memory move operations that do not modify code within the next 8 dwords. for more information on this instruction refer to chapter 5, ?scsi scripts instruction set.?
2-22 functional description ? on every store instruction. the store instruction may also be used to place modified code directly into memory. to avoid inadvertently flushing the prefetch unit contents use the no flush option for all store operations that do not modify code within the next 8 dwords. ? on every write to the dma scripts pointer (dsp) register. ? on all transfer control instructions when the transfer conditions are met. this is necessary because the next instruction to execute is not the sequential next instruction in the prefetch unit. ? whentheprefetchflushbit( dma control (dcntl) register, bit 6) is set. the unit flushes whenever this bit is set. the bit is self- clearing. 2.2.7 opcode fetch burst capability setting the burst opcode fetch enable bit (bit 1) in the dma mode (dmode) register (0x38) causes the LSI53C875A to burst in the first two dwords of all instruction fetches. if the instruction is a memory-to- memory move, the third dword is accessed in a separate ownership. if the instruction is an indirect type, the additional dword is accessed in a subsequent bus ownership. if the instruction is a table indirect block move, the chip uses two accesses to obtain the four dwords required, in two bursts of two dwords each. note: this feature is only useful if prefetching is disabled and scripts instructions are fetched from main memory. due to the short scripts ram access time, burst opcode fetching is not necessary when fetching instructions from this memory. 2.2.8 load and store instructions the LSI53C875A supports the load and store instruction type, which simplifies the movement of data between memory and the internal chip registers. it also enables the chip to transfer bytes to addresses relative to the data structure address (dsa) register. load and store data transfers to or from the scripts ram will remain internal to the chip and will not generate pci bus cycles. while a load/store to or from scripts ram is occurring, any external pci slave cycles that occur are retried on the pci bus. this feature can be disabled by setting the dils bit in the chip control 0 (ccntl0) register. for more information on the
scsi functional description 2-23 load and store instructions, refer to chapter 5, ?scsi scripts instruction set.? 2.2.9 jtag boundary scan testing the LSI53C875A includes support for jtag boundary scan testing in accordance with the ieee 1149.1 specification with one exception, which is explained in this section. this device accepts all required boundary scan instructions including the optional clamp, high-z, and idcode instructions. the LSI53C875A uses an 8-bit instruction register to support all boundary scan instructions. the data registers included in the device are the boundary data register, the idcode register, and the bypass register. this device can handle a 10 mhz tclk frequency for tdo and tdi. due to design constraints, the rst/ pin (system reset) always 3-states the scsi pins when it is asserted. boundary scan logic does not control this action, and this is not compliant with the specification. there are two solutions that resolve this issue: 1. use the rst/ pin as a boundary scan compliance pin. when the pin is deasserted, the device is boundary scan compliant and when asserted, the device is noncompliant. to maintain compliance the rst/pinmustbedrivenhigh. 2. when rst/ is asserted during boundary scan testing the expected output on the scsi pins must be the high-z condition, and not what is contained in the boundary scan data registers for the scsi pin output cells. 2.2.10 scsi loopback mode the LSI53C875A loopback mode allows testing of both initiator and target functions and, in effect, lets the chip communicate with itself. when the loopback enable bit is set in the scsi test two (stest2) register, bit 4, the LSI53C875A allows control of all scsi signals whether the chip is operating in the initiator or target mode. for more information on this mode of operation refer to the lsi logic scsi scripts processor programming guide .
2-24 functional description 2.2.11 parity options the LSI53C875A implements a flexible parity scheme that allows control of the parity sense, allows parity checking to be turned on or off, and has the ability to deliberately send a byte with bad parity over the scsi bus to test parity error recovery procedures. ta b l e 2 . 3 defines the bits that are involved in parity control and observation. ta b l e 2 . 4 describes the parity control function of the enable parity checking and assert scsi even parity bits in the scsi control one (scntl1) register, bit 2. ta b l e 2 . 5 describes the options available when a parity error occurs. figure 2.2 shows where parity checking is done in the LSI53C875A.
scsi functional description 2-25 table 2.3 bits used for parity control and generation bit name location description assert satn/ on parity errors scsi control zero (scntl0) ,bit1 causes the LSI53C875A to automatically assert satn/ when it detects a scsi parity error while operating as an initiator. enable parity checking scsi control zero (scntl0) ,bit3 enables the LSI53C875A to check for parity errors. the LSI53C875A checks for odd parity. assert even scsi parity scsi control one (scntl1) ,bit2 determines the scsi parity sense generated by the LSI53C875A to the scsi bus. disable halt on satn/ or a parity error (target mode only) scsi control one (scntl1) ,bit5 causes the LSI53C875A not to halt operations when a parity error is detected in target mode. enable parity error interrupt scsi interrupt enable zero (sien0) ,bit0 determines whether the LSI53C875A generates an interrupt when it detects a scsi parity error. parity error scsi interrupt status zero (sist0) ,bit0 this status bit is set whenever the LSI53C875A detects a parity error on the scsi bus. status of scsi parity signal scsi status zero (sstat0) ,bit0 this status bit represents the active high current state of the scsi sdp0 parity signal. scsi sdp1 signal scsi status two (sstat2) ,bit0 this bit represents the active high current state of the scsi sdp1 parity signal. latched scsi parity sstat 2, bit 3 and scsi status one (sstat1) ,bit3 these bits reflect the scsi odd parity signal corresponding to the data latched into the scsi input data latch (sidl) register. master parity error enable chip test four (ctest4) ,bit3 enables parity checking during pci master data phases. master data parity error dma status (dstat) ,bit6 set when the LSI53C875A , as a pci master, detects a target device signaling a parity error during a data phase. master data parity error interrupt enable dma interrupt enable (dien) , bit 6 by clearing this bit, a master data parity error does not cause assertion of inta/ (or intb/), but the status bit is set in the dma status (dstat) register.
2-26 functional description table 2.4 scsi parity control epc 1 1. epc = enable parity checking (bit 3 scsi control zero (scntl0) ). asep 2 2. asep = assert scsi even parity (bit 2 scsi control one (scntl1) ). description 0 0 does not check for parity errors. parity is generated when sending scsi data. asserts odd parity when sending scsi data. 0 1 does not check for parity errors. parity is generated when sending scsi data. asserts even parity when sending scsi data. 1 0 checks for odd parity on scsi data received. parity is generated when sending scsi data. asserts odd parity when sending scsi data. 1 1 checks for odd parity on scsi data received. parity is generated when sending scsi data. asserts even parity when sending scsi data. table 2.5 scsi parity errors and interrupts dhp 1 1. dhp = disable halt on satn/ or parity error (bit 5 scsi control one (scntl1) ). par 2 2. par = parity error (bit 0 scsi interrupt enable zero (sien0) ). description 0 0 halts when a parity error occurs in the target or initiator mode and does not generate an interrupt. 0 1 halts when a parity error occurs in the target mode and generates an interrupt in the target or initiator mode. 1 0 does not halt in target mode when a parity error occurs until the end of the transfer. an interrupt is not generated. 1 1 does not halt in target mode when a parity error occurs until the end of the transfer. an interrupt is generated.
scsi functional description 2-27 figure 2.2 parity checking/generation 2.2.12 dma fifo the dma fifo is 8 bytes wide by 118 transfers deep. the dma fifo is illustrated in figure 2.3 . the default dma fifo size is 112 bytes to assure compatibility with older products in the lsi53c8xx family. the dma fifo size may be set to 944 bytes by setting the dma fifo size bit, bit 5, in the chip test five (ctest5) register. pci interface** pci interface** pci interface** pci interface** dma fifo* (64 bits x 118) dma fifo* (64 bits x 118) dma fifo* (64 bits x 118) dma fifo* (64 bits x 118) sodl register* sidl register* sodl register* scsi fifo** (8 or 16 bits x 31) scsi interface** scsi interface** sodr register* scsi interface** scsi interface** ** = parity protected * = no parity protection asynchronous scsi send asynchronous scsi receive synchronous scsi send synchronous scsi receive x x x x x s s g g x = check parity g = generate 32-bit even pci parity s = generate 8-bit odd scsi parity
2-28 functional description figure 2.3 dma fifo sections the LSI53C875A automatically supports misaligned dma transfers. a 944-byte fifo allows the LSI53C875A to support 2, 4, 8, 16, 32, 64, or 128 dword bursts across the pci bus interface. 2.2.12.1 data paths the data path through the LSI53C875A is dependent on whether data is being moved into or out of the chip, and whether scsi data is being transferred asynchronously or synchronously. figure 2.4 shows how data is moved to/from the scsi bus in each of the different modes. 118 transfers deep . . . . . . 8 bytes wide 8bits byte lane 7 8bits byte lane 6 8bits byte lane 5 8bits byte lane 4 8bits byte lane 3 8bits byte lane 2 8bits byte lane 1 8bits byte lane 0
scsi functional description 2-29 figure 2.4 LSI53C875A host interface scsi data paths the following steps determine if any bytes remain in the data path when the chip halts an operation: asynchronous scsi send ? step 1. if the dma fifo size is set to 112 bytes (bit 5 of the chip test five (ctest5) register cleared), look at the dma fifo (dfifo) and dma byte counter (dbc) registers and calculate if there are bytes left in the dma fifo. to make this calculation, subtract the seven least significant bits of the dbc register from the 7-bit value of the dfifo register. and the result with 0x7f for a byte count between zero and 112. if the dma fifo size is set to 944 bytes (bit 5 of the chip test five (ctest5) register is set), subtract the 10 least significant pci interface** pci interface** pci interface** pci interface** dma fifo* (8 bytes x 118) dma fifo* (8 bytes x 118) dma fifo* (8 bytes x 118) dma fifo* (8 bytes x 118) sodl register* sidl register* sodl register* scsi fifo** (1 or 2 bytes x 31) scsi interface** scsi interface** sodr register* scsi interface** scsi interface** asynchronous scsi send asynchronous scsi receive synchronous scsi send synchronous scsi receive swide register swide register ** = parity protected * = no parity protection
2-30 functional description bits of the dbc register from the 10-bit value of the dma fifo byte offset counter, which consists of bits [1:0] in the ctest5 register and bits [7:0] of the dma fifo register. and the result with 0x3ff for a byte count between zero and 944. step 2. read bit 5 in the scsi status zero (sstat0) and scsi status tw o ( s s tat 2 ) registers to determine if any bytes are left in the scsi output data latch (sodl) register.ifbit5issetinthe sstat0 or sstat2 register, then the least significant byte or the most significant byte in the sodl register is full, respectively. checking this bit also reveals bytes left in the sodl register from a chained move operation with an odd byte count. synchronous scsi send ? step 1. if the dma fifo size is set to 112 bytes (bit 5 of the chip test five (ctest5) register cleared), look at the dfifo and dbc registers and calculate if there are bytes left in the dma fifo. to make this calculation, subtract the seven least significant bits of the dma byte counter (dbc) register from the 7-bit value of the dma fifo (dfifo) register. and the result with 0x7f for a byte count between zero and 112. if the dma fifo size is set to 944 bytes (bit 5 of the ctest5 register is set), subtract the 10 least significant bits of the dbc register from the 10-bit value of the dma fifo byte offset counter, which consists of bits [1:0] in the ctest5 register and bits [7:0] of the dma fifo register. and the result with 0x3ff for a byte count between zero and 944. step 2. read bit 5 in the scsi status zero (sstat0) and scsi status tw o ( s s tat 2 ) registers to determine if any bytes are left in the scsi output data latch (sodl) register.ifbit5issetinthe sstat0 or sstat2 register, then the least significant byte or the most significant byte in the sodl register is full, respectively. checking this bit also reveals bytes left in the sodl register from a chained move operation with an odd byte count. step 3. read bit 6 in the scsi status zero (sstat0) and scsi status tw o ( s s tat 2 ) registers to determine if any bytes are left in the sodr register (a hidden buffer register which is not accessible). if bit 6 is set in the sstat0 or sstat2 register,
scsi functional description 2-31 then the least significant byte or the most significant byte in the sodr register is full, respectively. asynchronous scsi receive ? step 1. if the dma fifo size is set to 112 bytes (bit 5 of the chip test five (ctest5) register cleared), look at the dma fifo (dfifo) and dma byte counter (dbc) registers and calculate if there are bytes left in the dma fifo. to make this calculation, subtract the seven least significant bits of the dbc register from the 7-bit value of the dfifo register. and the result with 0x7f for a byte count between zero and 88. if the dma fifo size is set to 944 bytes (bit 5 of the chip test five (ctest5) register is set), subtract the 10 least significant bits of the dma byte counter (dbc) register from the 10-bit value of the dma fifo byte offset counter, which consists of bits [1:0] in the ctest5 register and bits [7:0] of the dma fifo register. and the result with 0x3ff for a byte count between zero and 944. step 2. read bit 7 in the scsi status zero (sstat0) and scsi status tw o ( s s tat 2 ) registers to determine if any bytes are left in the scsi input data latch (sidl) register.ifbit7issetinthe sstat0 or sstat2 register, then the least significant byte or the most significant byte is full, respectively. step 3. if any wide transfers have been performed using the chained move instruction, read the wide scsi receive bit ( scsi status tw o ( s s tat 2 ) , bit 0) to determine whether a byte is left in the scsi wide residue (swide) register. synchronous scsi receive ? step 1. if the dma fifo size is set to 112 bytes, subtract the seven least significant bits of the dma byte counter (dbc) register from the 7-bit value of the dma fifo (dfifo) register. and the result with 0x7f for a byte count between zero and 112. if the dma fifo size is set to 944 bytes (bit 5 of the chip test five (ctest5) register is set), subtract the 10 least significant bits of the dbc register from the 10-bit value of the dma fifo byte offset counter, which consists of bits [1:0] in the chip test five (ctest5) register and bits [7:0] of the dma fifo register.
2-32 functional description and the result with 0x3ff for a byte count between zero and 944. step 2. read the scsi status one (sstat1) register and examine bits [7:4], the binary representation of the number of valid bytes in the scsi fifo, to determine if any bytes are left in the scsi fifo. step 3. if any wide transfers have been performed using the chained move instruction, read the wide scsi receive bit ( scsi control two (scntl2) , bit 0) to determine whether a byte is left in the scsi wide residue (swide) register. 2.2.13 scsi bus interface the LSI53C875A performs se transfers. tolerant technology provides signal filtering at the inputs of sreq/ and sack/ to increase immunity to signal reflections. 2.2.13.1 scsi termination the terminator networks provide the biasing needed to pull signals to an inactive voltage level. they also match the impedance seen at the end of the cable with the characteristic impedance of the cable. terminators must be installed at the extreme ends of the scsi chain and only at the ends. no system should ever have more or less than two terminators installed and active. scsi host adapters should provide a means of accommodating terminators. the terminators should be socketed, so that if not needed they may be removed, or there should be a means of disabling them with software. se cables can use a 220 ? pull-up to the terminator power supply (term power) line and a 330 ? pull-down to ground. due to the high performance nature of the LSI53C875A, regulated or active termination is recommended. figure 2.5 shows a unitrode active terminator. for additional information, refer to the scsi-2 specification. tolerant technology active negation can be used with either termination network. note : iftheLSI53C875Aisusedwithan8-bitscsibus,all 16 data lines must still be terminated or pulled high. note : active termination is required for ultra scsi synchronous transfers.
scsi functional description 2-33 figure 2.5 regulated termination for ultra scsi 2.2.14 select/reselect during selection/reselection in multithreaded scsi i/o environments, it is not uncommon to be selected or reselected while trying to perform selection/reselection. this terml1 terml2 terml3 terml4 terml5 terml6 terml7 terml8 terml9 terml10 terml11 terml12 terml13 terml14 terml15 terml16 terml17 terml18 sd0 (j1.40) sd1 (j1.41) sd2 (j1.42) sd3 (j1.43) sd4 (j1.44) sd5 (j1.45) sd6 (j1.46) sd7 (j1.47) sdp0 (j1.48) atn (j1.55) bsy (j1.57) ack (j1.58) rst (j1.59) msg (j1.60) sel (j1.61) c/d (j1.62) req (j1.63) i/o (j1.64) 20 21 22 23 24 25 26 27 28 3 4 5 6 7 8 9 10 11 19 disconnect reg_out 2 2.85 v uc5601qp c1 c2 note: 1. c1 - 10 fsmt 2. c2 - 0.1 fsmt 3. c3 - 2.2 fsmt 4. j1 - 68-pin, high density ?p? connector terml1 terml2 terml3 terml4 terml5 terml6 terml7 terml8 terml9 sd15 (j1.38) sd14 (j1.37) sd13 (j1.36) sd12 (j1.35) sd11 (j1.68) sd10 (j1.67) sd9 (j1.66) sd8 (j1.65) sdp1 (j1.39) 10 9 8 7 3 2 1 16 15 reg_out 14 uc5603dp c3 6 disconnect (uc5614 for ultra scsi) (uc5610 for ultra scsi)
2-34 functional description situation may occur when a scsi controller (operating in the initiator mode) tries to select a target and is reselected by another. the select scripts instruction has an alternate address to which the scripts will jump when this situation occurs. the analogous situation for target devices is being selected while trying to perform a reselection. once a change in operating mode occurs, the initiator scripts should start with a set initiator instruction or the target scripts should start with a set target instruction. the selection and reselection enable bits ( scsi chip id (scid) bits 5 and 6, respectively) should both be asserted so that the LSI53C875A may respond as an initiator or as a target. if only selection is enabled, the LSI53C875A cannot be reselected as an initiator. there are also status and interrupt bits in the scsi interrupt status zero (sist0) and scsi interrupt enable zero (sien0) registers, respectively, indicating that the LSI53C875A has been selected (bit 5) and reselected (bit 4). 2.2.15 synchronous operation the LSI53C875A can transfer synchronous scsi data in both the initiator and target modes. the scsi transfer (sxfer) register controls both the synchronous offset and the transfer period. it may be loaded by the cpu before scripts execution begins, from within scripts using a table indirect i/o instruction, or with a read-modify-write instruction. the LSI53C875A can receive data from the scsi bus at a synchronous transfer period as short as 50 ns, regardless of the transfer period used to send data. the LSI53C875A can receive data at one-fourth of the divided sclk frequency. depending on the sclk frequency, the negotiated transfer period, and the synchronous clock divider, the LSI53C875A can send synchronous data at intervals as short as 50 ns for ultra scsi, 100 ns for fast scsi and 200 ns for scsi-1. 2.2.15.1 determining the data transfer rate synchronous data transfer rates are controlled by bits in two different registers of the LSI53C875A. following is a brief description of the bits. figure 2.6 illustrates the clock division factors used in each register, and the role of the register bits in determining the transfer rate.
scsi functional description 2-35 figure 2.6 determining the synchronous transfer rate sclk clock quadrupler qclk scf divider ccf divider synchronous divider asynchronous scsi logic divide by 4 scf2 scf1 scf0 scf divisor 0011 0101.5 0112 1003 0003 1014 1106 1118 tp2 tp1 tp0 xferp divisor 0004 0015 0106 0117 1008 1019 11010 11111 ccf2 ccf1 ccf0 divisor qclk (mhz) 0 0 1 1 50.1?66.00 0 1 0 1.5 16.67?25.00 0 1 1 2 25.1?37.50 1 0 0 3 37.51?50.00 0 0 0 3 50.01?66.00 1 0 1 4 75.01?80.00 1 1 0 6 120 1 1 1 8 160 example 1 (using 40 mhz clock) qclk (quadrupled scsi clock) = 160 mhz scf = 1 (/1), xferp = 4 (/8), ccf = 7 (/8) synchronous send rate = (qclk/scf)/xferp = (160/1) /8 1 = 20 mbytes/s synchronous receive rate = (qclk/scf) /4 = (160/1) /4 2 = 40 mbytes/s this point must not exceed 160 mhz receive clock send clock (to scsi bus) this point must not exceed 20 mhz. sclk = 40 mhz example 2 (using 20 mhz clock) qclk (quadrupled scsi clock) = 80 mhz scf = 1 (/1), xferp = 0 (/4), ccf = 5 (/4) synchronous send rate = (qclk/scf)/xferp = (80/1) /4 = 20 mbytes/s synchronous receive rate = (qclk/scf) /4 = (80/1) /4 = 20 mbytes/s sclk = 20 mhz note: ? synchronous send rate must not exceed 20 mbytes/s because the LSI53C875A is an ultra scsi device. ? although maximum synchronous receive rate is 40 mbytes/s the maximum transfer rate is 20 mbytes/s because the LSI53C875A is an ultra scsi device.
2-36 functional description 2.2.15.2 scsi control three (scntl3) register, bits [6:4] (scf[2:0]) the scf[2:0] bits select the factor by which the frequency of sclk is divided before being presented to the synchronous scsi control logic. the output from this divider controls the rate at which data can be received; this rate must not exceed 160 mhz. the receive rate of synchronous scsi data is one-fourth of the scf divider output. for example, if sclk is 80 mhz and the scf value is set to divide by one, then the maximum rate at which data can be received is 20 mhz (80/(1*4) = 20). 2.2.15.3 scsi control three (scntl3) register, bits [2:0] (ccf[2:0]) the ccf[2:0] bits select the factor by which the frequency of sclk is divided before being presented to the asynchronous scsi core logic. this divider must be set according to the input clock frequency in the table. 2.2.15.4 scsi transfer (sxfer) register, bits [7:5] (tp[2:0]) the tp[2:0] divider bits determine the scsi synchronous transfer period when sending synchronous scsi data in either the initiator or target mode. this value further divides the output from the scf divider. 2.2.15.5 ultra scsi synchronous data transfers ultra scsi is an extension of the current fast scsi-2 synchronous transfer specifications. it allows synchronous transfer periods to be negotiated down as low as 50 ns, which is half the 100 ns period allowed under fast scsi-2. this allows a maximum transfer rate of 40 mbytes/s on a 16-bit scsi bus. the LSI53C875A has a scsi clock quadrupler that must be enabled for the chip to perform ultra scsi transfers with a 20 or 40 mhz oscillator. in addition, the following bit values affect the chip?s ability to support ultra scsi synchronous transfer rates: ? clock conversion factor bits, scsi control three (scntl3) register bits [2:0] and synchronous clock conversion factor bits, scntl3 register bits [6:4]. these fields support a value of 111 (binary), allowing the 160 mhz sclk frequency to be divided by 8 for the asynchronous logic.
scsi functional description 2-37 ? ultra scsi enable bit, scsi control three (scntl3) register bit 7. setting this bit enables ultra scsi synchronous transfers in systems that use the internal scsi clock quadrupler. ? tolerant enable bit, scsi test three (stest3) register bit 7. active negation must be enabled for the LSI53C875A to perform ultra scsi transfers. 2.2.16 interrupt handling the scripts processors in the LSI53C875A perform most functions independently of the host microprocessor. however, certain interrupt situations must be handled by the external microprocessor. this section explains all aspects of interrupts as they apply to the LSI53C875A. 2.2.16.1 polling and hardware interrupts the external microprocessor is informed of an interrupt condition by polling or hardware interrupts. polling means that the microprocessor must continually loop and read a register until it detects a bit that is set indicating an interrupt. this method is the fastest, but it wastes cpu time that could be used for other system tasks. the preferred method of detecting interrupts in most systems is hardware interrupts. in this case, the LSI53C875A asserts the interrupt request (irq/) line that interrupts the microprocessor, causing the microprocessor to execute an interrupt service routine. a hybrid approach would use hardware interrupts for long waits, and use polling for short waits. 2.2.16.2 registers the registers in the LSI53C875A that are used for detecting or defining interrupts are interrupt status zero (istat0) , interrupt status one (istat1) , mailbox zero (mbox0) , mailbox one (mbox1) , scsi interrupt status zero (sist0) , scsi interrupt status one (sist1) , dma status (dstat) , scsi interrupt enable zero (sien0) , scsi interrupt enable one (sien1) , dma control (dcntl) ,and dma interrupt enable (dien) . istat ? the istat register includes the interrupt status zero (istat0) , interrupt status one (istat1) , chip test zero (ctest0) ,and mailbox one (mbox1) registers. it is the only register that can be accessed as a slave during the scripts operation. therefore, it is the register that is
2-38 functional description polled when polled interrupts are used. it is also the first register that should be read after the irq/ pin is asserted in association with a hardware interrupt. the intf (interrupt-on-the-fly) bit should be the first interrupt serviced. it must be written to one to be cleared. this interrupt must be cleared before servicing any other interrupts. see register 0x14, interrupt status zero (istat0) register, bit 5 signal process in chapter 4, ?registers,? for additional information. the host (c code) or the scripts code could potentially try to access the mailbox bits at the same time. if the sip bit in the interrupt status zero (istat0) register is set, then a scsi-type interrupt has occurred and the scsi interrupt status zero (sist0) and scsi interrupt status one (sist1) registers should be read. if the dip bit in the interrupt status zero (istat0) register is set, then a dma-type interrupt has occurred and the dma status (dstat) register should be read. scsi-type and dma-type interrupts may occur simultaneously, so in some cases both sip and dip may be set. sist0 and sist1 ? the scsi interrupt status zero (sist0) and scsi interrupt status one (sist1) registers contain scsi-type interrupt bits. reading these registers determines which condition or conditions caused the scsi-type interrupt, and clears that scsi interrupt condition. if the LSI53C875A is receiving data from the scsi bus and a fatal interrupt condition occurs, the chip attempts to send the contents of the dma fifo to memory before generating the interrupt. if the LSI53C875A is sending data to the scsi bus and a fatal scsi interrupt condition occurs, data could be left in the dma fifo. because of this the dma fifo empty (dfe) bit in dma status (dstat) should be checked. if this bit is cleared, set the clf (clear dma fifo) and csf (clear scsi fifo) bits before continuing. the clf bit is bit 2 in chip test three (ctest3) . the csf bit is bit 1 in scsi test three (stest3) . dstat ? the dma status (dstat) register contains the dma-type interrupt bits. reading this register determines which condition or
scsi functional description 2-39 conditions caused the dma-type interrupt, and clears that dma interrupt condition. bit 7 in dstat, dfe, is purely a status bit; it will not generate an interrupt under any circumstances and will not be cleared when read. dma interrupts flush neither the dma nor scsi fifos before generating the interrupt, so the dfe bit in the dma status (dstat) register should be checked after any dma interrupt. if the dfe bit is cleared, then the fifos must be cleared by setting the clf (clear dma fifo) and csf (clear scsi fifo) bits, or flushed by setting the flf (flush dma fifo) bit. sien0 and sien1 ? the scsi interrupt enable zero (sien0) and scsi interrupt enable one (sien1) registers are the interrupt enable registers for the scsi interrupts in scsi interrupt status zero (sist0) and scsi interrupt status one (sist1) . dien ? the dma interrupt enable (dien) register is the interrupt enable register for dma interrupts in dma status (dstat) . dcntl ? when bit 1 in the dma control (dcntl) register is set, the irq/ pin is not asserted when an interrupt condition occurs. the interrupt is not lost or ignored, but is merely masked at the pin. clearing this bit when an interrupt is pending immediately causes the irq/ pin to assert. as with any register other than istat, this register cannot be accessed except by a scripts instruction during scripts execution. 2.2.16.3 fatal vs. nonfatal interrupts a fatal interrupt, as the name implies, always causes the scripts to stop running. all nonfatal interrupts become fatal when they are enabled by setting the appropriate interrupt enable bit. interrupt masking is discussed in section 2.2.16.4, ?masking.? all dma interrupts (indicated by the dip bit in istat and one or more bits in dma status (dstat) being set) are fatal. some scsi interrupts (indicated by the sip bit in the interrupt status zero (istat0) and one or more bits in scsi interrupt status zero (sist0) or scsi interrupt status one (sist1) being set) are nonfatal. when the LSI53C875A is operating in the initiator mode, only the function complete (cmp), selected (sel), reselected (rsl), general
2-40 functional description purpose timer expired (gen), and handshake-to-handshake timer expired (hth) interrupts are nonfatal. when operating in the target mode, cmp, sel, rsl, target mode: satn/ active (m/a), gen, and hth are nonfatal. refer to the description for the disable halt on a parity error or satn/ active (target mode only) (dhp) bit in the scsi control one (scntl1) register to configure the chip?s behavior when the satn/ interrupt is enabled during target mode operation. the interrupt-on-the-fly interrupt is also nonfatal, since scripts can continue when it occurs. the reason for nonfatal interrupts is to prevent the scripts from stopping when an interrupt occurs that does not require service from the cpu. this prevents an interrupt when arbitration is complete (cmp set), when the LSI53C875A is selected or reselected (sel or rsl set), when the initiator asserts atn (target mode: satn/ active), or when the general purpose or handshake-to-handshake timers expire. these interrupts are not needed for events that occur during high-level scripts operation. 2.2.16.4 masking masking an interrupt means disabling or ignoring that interrupt. interrupts canbemaskedbyclearingbitsinthe scsi interrupt enable zero (sien0) and scsi interrupt enable one (sien1) (for scsi interrupts) registers or dma interrupt enable (dien) (for dma interrupts) register. how the chip responds to masked interrupts depends on: whether polling or hardware interrupts are being used; whether the interrupt is fatal or nonfatal; and whether the chip is operating in the initiator or target mode. if a nonfatal interrupt is masked and that condition occurs, the scripts do not stop, the appropriate bit in the scsi interrupt status zero (sist0) or scsi interrupt status one (sist1) is still set, the sip bit in the interrupt status zero (istat0) is not set, and the irq/ pin is not asserted. if a fatal interrupt is masked and that condition occurs, then the scripts still stop, the appropriate bit in the dma status (dstat) , scsi interrupt status zero (sist0) ,or scsi interrupt status one (sist1) register is set, and the sip or dip bit in the interrupt status zero (istat0) register is set, but the irq/ pin is not asserted.
scsi functional description 2-41 interrupts can be disabled by setting sync_irqd bit 0 in the interrupt status one (istat1) register. if an interrupt is already asserted and sync_irqd is then set, the interrupt will remain asserted until serviced. at this point, the irq/ pin is blocked for future interrupts until this bit is cleared. when the LSI53C875A is initialized, enable all fatal interrupts if you are using hardware interrupts. if a fatal interrupt is disabled and that interrupt condition occurs, the scripts halt and the system never knows it unless it times out and checks the istat register after a certain period of inactivity. if you are polling the istat instead of using hardware interrupts, then masking a fatal interrupt makes no difference since the sip and dip bits in the interrupt status zero (istat0) inform the system of interrupts, not the irq/ pin. masking an interrupt after irq/ is asserted does not cause deassertion of irq/. 2.2.16.5 stacked interrupts the LSI53C875A will stack interrupts if they occur one after the other. if the sip or dip bits in the istat register are set (first level), then there is already at least one pending interrupt, and any future interrupts are stacked in extra registers behind the scsi interrupt status zero (sist0) , scsi interrupt status one (sist1) , and dma status (dstat) registers (second level). when two interrupts have occurred and the two levels of the stack are full, any further interrupts set additional bits in the extra registers behind scsi interrupt status zero (sist0) , scsi interrupt status one (sist1) , and dma status (dstat) . when the first level of interrupts are cleared, all the interrupts that came in afterward move into sist0, sist1, and dstat. after the first interrupt is cleared by reading the appropriate register, the irq/ pin is deasserted for a minimum of three clks; the stacked interrupts move into sist0, sist1, or dstat; and the irq/ pin is asserted once again. since a masked nonfatal interrupt does not set the sip or dip bits, interrupt stacking does not occur. a masked, nonfatal interrupt still posts the interrupt in sist0, but does not assert the irq/ pin. since no interrupt is generated, future interrupts move into scsi interrupt status zero (sist0) or scsi interrupt status one (sist1) instead of being stacked behind another interrupt. when another condition occurs that
2-42 functional description generates an interrupt, the bit corresponding to the earlier masked nonfatal interrupt is still set. a related situation to interrupt stacking is when two interrupts occur simultaneously. since stacking does not occur until the sip or dip bits are set, there is a small timing window in which multiple interrupts can occur but are not stacked. these could be multiple scsi interrupts (sip set), multiple dma interrupts (dip set), or multiple scsi and multiple dma interrupts (both sip and dip set). as previously mentioned, dma interrupts do not attempt to flush the fifos before generating the interrupt. it is important to set either the clear dma fifo (clf) and clear scsi fifo (csf) bits if a dma interrupt occurs and the dma fifo empty (dfe) bit is not set. this is because any future scsi interrupts are not posted until the dma fifo is cleared of data. these ?locked out? scsi interrupts are posted as soon as the dma fifo is empty. 2.2.16.6 halting in an orderly fashion when an interrupt occurs, the LSI53C875A attempts to halt in an orderly fashion. ? if the interrupt occurs in the middle of an instruction fetch, the fetch is completed, except in the case of a bus fault. execution does not begin, but the dma scripts pointer (dsp) points to the next instruction since it is updated when the current instruction is fetched. ? if the dma direction is a write to memory and a scsi interrupt occurs, the LSI53C875A attempts to flush the dma fifo to memory before halting. under any other circumstances only the current cycle is completed before halting, so the dfe bit in dma status (dstat) register should be checked to see if any data remains in the dma fifo. ? scsi sreq/sack handshakes that have begun are completed before halting. ? the LSI53C875A attempts to clean up any outstanding synchronous offset before halting. ? in the case of transfer control instructions, once instruction execution begins it continues to completion before halting.
scsi functional description 2-43 ? if the instruction is a jump/call when/if , the dma scripts pointer (dsp) is updated to the transfer address before halting. ? all other instructions may halt before completion. 2.2.16.7 sample interrupt service routine the following is a sample of an interrupt service routine for the LSI53C875A. it can be repeated during polling or should be called when the irq/ pin is asserted during hardware interrupts. 1. read interrupt status zero (istat0) . 2. if the intf bit is set, it must be written to a one to clear this status. 3. if only the sip bit is set, read scsi interrupt status zero (sist0) and scsi interrupt status one (sist1) to clear the scsi interrupt condition and get the scsi interrupt status. the bits in the sist0 and sist1 tell which scsi interrupts occurred and determine what action is required to service the interrupts. 4. if only the dip bit is set, read dma status (dstat) to clear the interrupt condition and get the dma interrupt status. the bits in dstat tell which dma interrupts occurred and determine what action is required to service the interrupts. 5. if both the sip and dip bits are set, read scsi interrupt status zero (sist0) , scsi interrupt status one (sist1) ,and dma status (dstat) to clear the scsi and dma interrupt condition and get the interrupt status. if using 8-bit reads of the sist0, sist1, and dstat registers to clear interrupts, insert a 12 clk delay between the consecutive reads to ensure that the interrupts clear properly. both the scsi and dma interrupt conditions should be handled before leaving the interrupt service routine. it is recommended that the dma interrupt is serviced before the scsi interrupt, because a serious dma interrupt condition could influence how the scsi interrupt is acted upon. 6. when using polled interrupts, go back to step 1 before leaving the interrupt service routine, in case any stacked interrupts moved in when the first interrupt was cleared. when using hardware interrupts, the irq/ pin is asserted again if there are any stacked interrupts. this should cause the system to re-enter the interrupt service routine.
2-44 functional description 2.2.17 chained block moves since the LSI53C875A has the capability to transfer 16-bit wide scsi data, a unique situation occurs when dealing with odd bytes. the chained move (chmov) scripts instruction along with the wide scsi send (wss) and wide scsi receive (wsr) bits in the scsi control two (scntl2) register are used to facilitate these situations. the chained block move instruction is illustrated in figure 2.7 .
scsi functional description 2-45 figure 2.7 block move and chained block move instructions 2.2.17.1 wide scsi send bit the wss bit is set whenever the scsi controller is sending data (data-out for initiator or data-in for target) and the controller detects a partial transfer at the end of a chained block move scripts instruction (this flag is not set if a normal block move instruction is used). under this condition, the scsi controller does not send the low-order byte of the last partial memory transfer across the scsi bus. instead, the low-order byte is temporarily stored in the lower byte of the scsi output data latch (sodl) register and the wss flag is set. the hardware uses the wss flag to determine what behavior must occur at the start of the next data send transfer. when the wss flag is set at the start of the next transfer, the first byte (the high-order byte) of the next data send transfer is ?married? with the stored low-order byte in the sodl register; and the 0x02 0x01 0x00 0x0b 0x0a 0x09 0x08 0x0f 0x0e 0x0d 0x0c 0x13 0x12 0x11 0x10 0x09 0x0b 0x0a 0x0d 0x0c 0x07 0x06 0x05 0x04 0x04 0x03 0x06 0x05 0x07 host memory scsi bus 32 bits 16 bits 0x03
2-46 functional description two bytes are sent out across the bus, regardless of the type of block move instruction (normal or chained). the flag is automatically cleared when the ?married? word is sent. the flag is alternately cleared through scripts or by the microprocessor. also, the microprocessor or scripts can use this bit for error detection and recovery purposes. 2.2.17.2 wide scsi receive bit the wsr bit is set whenever the scsi controller is receiving data (data-in for initiator or data-out for target) and the controller detects a partial transfer at the end of a block move or chained block move scripts instruction. when wsr is set, the high-order byte of the last scsi bus transfer is not transferred to memory. instead, the byte is temporarily stored in the scsi wide residue (swide) register. the hardware uses the wsr bit to determine what behavior must occur at the start of the next data receive transfer. the bit is automatically cleared at the start of the next data receive transfer. the bit can alternatively be cleared by the microprocessor or through scripts. also, the microprocessor or scripts can use this bit for error detection and recovery purposes. 2.2.17.3 swide register this register stores data for partial byte data transfers. for receive data, the scsi wide residue (swide) register holds the high-order byte of a partial scsi transfer which has not yet been transferred to memory. this stored data may be a residue byte (and therefore ignored) or it may be valid data that is transferred to memory at the beginning of the next block move instruction. 2.2.17.4 sodl register for send data, the low-order byte of the scsi output data latch (sodl) register holds the low-order byte of a partial memory transfer which has not yet been transferred across the scsi bus. this stored data is usually ?married? with the first byte of the next data send transfer, and both bytes are sent across the scsi bus at the start of the next data send block move command.
scsi functional description 2-47 2.2.17.5 chained block move scripts instruction a chained block move scripts instruction is primarily used to transfer consecutive data send or data receive blocks. using the chained block move instruction facilitates partial receive transfers and allows correct partial send behavior without additional opcode overhead. behavior of the chained block move instruction varies slightly for sending and receiving data. for receive data (data-in for initiator or data-out for target), a chained block move instruction indicates that if a partial transfer occurred at the end of the instruction, the wsr flag is set. the high-order byte of the last scsi transfer is stored in the scsi wide residue (swide) register rather than transferred to memory. the contents of the swide register should be the first byte transferred to memory at the start of the chained block move data stream. since the byte count always represents data transfers to/from memory (as opposed to the scsi bus), the byte transferred out of the scsi wide residue (swide) register is one of the bytes in the byte count. if the wsr bit is cleared when a receive data chained block move instruction is executed, the data transfer occurs similar to that of the regular block move instruction. whether the wsr bit is set or cleared, when a normal block move instruction is executed, the contents of the scsi wide residue (swide) register are ignored and the transfer takes place normally. for ?n? consecutive wide data receive block move instructions, the 2nd through the nth block move instructions should be chained block moves. for send data (data-out for initiator or data-in for target), a chained block move instruction indicates that if a partial transfer terminates the chained block move instruction, the last low-order byte (the partial memorytransfer)shouldbestoredinthelowerbyteofthe scsi output data latch (sodl) register and not sent across the scsi bus. without the chained block move instruction, the last low-order byte would be sent across the scsi bus. the starting byte count represents data bytes transferred from memory but not to the scsi bus when a partial transfer exists. for example, if the instruction is an initiator chained block move data out of five bytes (and wss is not previously set), five bytes are transferred out of memory to the scsi controller, four bytes are transferred from the scsi controller across the scsi bus, and one byte is temporarily stored in the lower byte of the scsi output data latch (sodl) register waiting to be married with the first byte of the next block move instruction. regardless of whether a chained block move or normal block move instruction is used, if the wss bit is set at the start of a data
2-48 functional description send command, the first byte of the data send command is assumed to be the high-order byte and is ?married? with the low-order byte stored in the lower byte of the scsi output data latch (sodl) register before the two bytes are sent across the scsi bus. for ?n? consecutive wide data send block move commands, the first through the (n th ? 1) block move instructions should be chained block moves. chmov 5, 3 when data_out moves five bytes from address 0x03 in the host memory to the scsi bus. bytes 0x03, 0x04, 0x05, and 0x06 are moved and byte 0x07 remains in the low-order byte of the scsi output data latch (sodl) register and ismarriedwiththefirstbyteofthefollowingmoveinstruction. move 5, 9 when data_out moves five bytes from address 0x09 in the host memory to the scsi bus. 2.3 parallel rom interface the LSI53C875A supports up to one megabyte of external memory in binary increments from 16 kbytes, to allow the use of expansion rom for add-in pci cards. this interface is designed for low speed operations such as downloading instruction code from rom; it is not intended for dynamic activities such as executing instructions. system requirements include the LSI53C875A, two or three external 8-bit address holding registers (hct273 or hct374), and the appropriate memory device. the 4.7 k ? pull-up resistors on the mad bus require hc or hct external components to be used. if in-system flash rom updates are required, a 7406 (high voltage open collector inverter), a mtd4p05, and several passive components are also needed. the memory size and speed is determined by pull-up resistors on the 8-bit bidirectional memory bus at power-up. the LSI53C875A senses this bus shortly after the release of the reset signal and configures the expansion rom base address register and the memory cycle state machines for the appropriate conditions. the external memory interface works with a variety of rom sizes and speeds. an example set of interface drawings is in appendix b, ?external memory interface diagram examples.?
parallel rom interface 2-49 the LSI53C875A supports a variety of sizes and speeds of expansion rom, using pull-down resistors on the mad[3:0] pins. the encoding of pins mad[3:1] allows the user to define how much external memory is available to the LSI53C875A. ta b l e 2 . 6 shows the memory space associated with the possible values of mad[3:1]. the mad[3:1] pins are fully described in chapter 3, ?signal descriptions.? to use one of the configurations mentioned above in a host adapter board design, put 4.7 k ? pull-up resistors on the mad pins corresponding to the available memory space. for example, to connect to a 64 kbyte external rom, use a pull-up on mad2. if the external memory interface is not used, mad[3:1] should be pulled high. note: there are internal pull-downs on all of the mad bus signals. the LSI53C875A allows the system to determine the size of the available external memory using the expansion rom base address register in the pci configuration space. for more information on how this works, refer to the pci specification or the expansion rom base address register description in chapter 4, ?registers.? mad0 is the slow rom pin. when pulled up, it enables two extra clock cycles of data access time to allow use of slower memory devices. the external memory interface also supports updates to flash memory. table 2.6 parallel rom support mad[3:1] available memory space 000 16 kbytes 001 32 kbytes 010 64 kbytes 011 128 kbytes 100 256 kbytes 101 512 kbytes 110 1024 kbytes 111 no external memory present
2-50 functional description 2.4 serial eeprom interface the LSI53C875A implements an interface that allows attachment of a serial eeprom device to the gpio0 and gpio1 pins. there are two modes of operation relating to the serial eeprom and the subsystem id and subsystem vendor id registers. these modes are programmable through the mad7 pin which is sampled at power-up. 2.4.1 default download mode in this mode, mad7 is pulled down internally, gpio0 is the serial data signal (sda) and gpio1 is the serial clock signal (scl). certain data in the serial eeprom is automatically loaded into chip registers at power-up. the format of the serial eeprom data is defined in ta b l e 2 . 7 .ifthe download is enabled and an eeprom is not present, or the checksum fails, the subsystem id and subsystem vendor id registers read back all zeros. at power-up, only five bytes are loaded into the chip from locations 0xfb through 0xff. the subsystem id and subsystem vendor id registers are read only, in accordance with the pci specification, with a default value of all zeros if the download fails.
power management 2-51 2.4.2 no download mode when mad7 is pulled up through an external resistor, the automatic download is disabled and no data is automatically loaded into chip registers at power-up. the subsystem id and subsystem vendor id registers are read only, per the pci specification, with a default value of 0x1000 and 0x1000 respectively. 2.5 power management the LSI53C875A complies with the pci bus power management interface specification, revision 1.1. the pci function power states d0, d1, d2, and d3 are defined in that specification. d0 is the maximum powered state, and d3 is the minimum powered state. power state d3 is further categorized as d3hot or d3cold. a function that is powered off is said to be in the d3cold power state. table 2.7 mode a serial eeprom data format byte name description 0xfb svid(0) subsystem vendor id , lsb. this byte is loaded into the least significant byte of the subsystem vendor id register in the appropriate pci configuration space at chip power-up. 0xfc svid(1) subsystem vendor id, msb. this byte is loaded into the most significant byte of the subsystem vendor id register in the appropriate pci configuration space at chip power-up. 0xfd sid(0) subsystem id , lsb. this byte is loaded into the least significant byte of the subsystem id register in the appropriate pci configuration space at chip power-up. 0xfe sid(1) subsystem id, msb. this byte is loaded into the most significant byte of the subsystem id register in the appropriate pci configuration space at chip power-up. 0xff cksum checksum. this 8-bit checksum is formed by adding, bytewise, each byte contained in locations 0x00?0x03 to the seed value 0x55, and then taking the 2s complement of the result. 0x100?0xeom ud user data.
2-52 functional description the LSI53C875A power states shown in ta bl e 2 . 8 are independently controlled through two power state bits that are located in the pci power management control/status (pmcsr) register 0x44. although the pci bus power management interface specification does not allow power state transitions d2 to d1, d3 to d2, or d3 to d1, the LSI53C875A hardware places no restriction on transitions between power states. as the device transitions from one power level to a lower one, the attributes that occur from the higher power state level are carried over into the lower power state level. for example, d1 disables the scsi clk. therefore, d2 will include this attribute as well as the attributes defined in the power state d2 section. the pci function power states d0, d1, d2, and d3 are described below. power state actions are separate for each function. 2.5.1 power state d0 power state d0 is the maximum power state and is the power-up default state. the LSI53C875A is fully functional in this state. 2.5.2 power state d1 power state d1 is a lower power state than d0. in this state, the LSI53C875A core is placed in the snooze mode and the scsi clk is disabled. in the snooze mode, a scsi reset does not generate an irq/ signal. however, the scsi clk is still disabled. table 2.8 power states configuration register 0x44 bits [1:0] power state function 00 d0 maximum power 01 d1 disables scsi clock 10 d2 coma mode 11 d3 minimum power
power management 2-53 2.5.3 power state d2 power state d2 is a lower power state than d1. in this state the LSI53C875A core is placed in the coma mode. the following pci configuration space command register enable bits are suppressed: ? i/o space enable ? memory space enable ? bus mastering enable ? serr/enable ? enable parity error response thus, the memory and i/o spaces cannot be accessed, and the LSI53C875A cannot be a pci bus master. furthermore, all interrupts are disabled when in power state d2. if changed from power state d2 to power state d0, the previous values of the pci command register are restored. also, any pending interrupts before the function entered power state d2 are asserted. 2.5.4 power state d3 power state d3 is the minimum power state, which includes settings called d3hot and d3cold. d3hot allows the device to transition to d0 using software. the LSI53C875A is considered to be in power state d3cold when power is removed from the device. d3cold can transition to d0 by applying v cc and resetting the device. furthermore, the device's soft reset is continually asserted while in power state d3, which clears all pending interrupts and 3-states the scsi bus. in addition, the device's pci command register is cleared and the clock quadrupler is disabled, which results in additional power savings.
2-54 functional description
LSI53C875A pci to ultra scsi controller 3-1 chapter 3 signal descriptions this chapter presents the LSI53C875A pin configuration and signal definitions using tables and illustrations. this chapter contains the following sections: ? section 3.1, ?LSI53C875A functional signal grouping? ? section 3.2, ?signal descriptions? ? section 3.3, ?pci bus interface signals? ? section 3.4, ?scsi bus interface signals? ? section 3.5, ?gpio signals? ? section 3.6, ?rom flash and memory interface signals? ? section 3.7, ?test interface signals? ? section 3.8, ?power and ground signals? ? section 3.9, ?mad bus programming? a slash (/) at the end of a signal name indicates that the active state occurs when the signal is at a low voltage. when the slash is absent, the signal is active at a high voltage.
3-2 signal descriptions 3.1 LSI53C875A functional signal grouping figure 3.1 presents the LSI53C875A signals by functional group. figure 3.1 LSI53C875A functional signal grouping LSI53C875A clk rst/ ad[31:0] c_be[3:0]/ pa r frame/ trdy/ irdy/ stop/ devsel/ idsel req/ gnt/ perr/ serr/ irq/ gpio0_fetch/ gpio1_master/ gpio2 gpio3 gpio4 mwe/ mce/ moe/ mac/_testout mas0/ mas1/ mad[7:0] sclk sd[15:0] sdp[1:0] scd sio smsg sreq sack sbsy satn srst ssel test_rst/ test_hsc/ mac/_testout tck tms tdi tdo system address and data interface control arbitration error reporting interrupt rom flash & memory interface scsi scsi bus interface te s t interface pci bus interface trst/ scsi function gpio
signal descriptions 3-3 3.2 signal descriptions the signal descriptions are divided into pci bus interface signals , scsi bus interface signals , gpio signals, rom flash and memory interface signals , test interface signals ,and power and ground signals . the pci bus interface signals are subdivided into system signals , address and data signals , interface control signals , arbitration signals , error reporting signals , and interrupt signal . the scsi bus interface signals are subdivided into scsi bus interface signals , scsi signals ,and scsi control signals . signals are assigned a type. there are five signal types: 3.2.1 internal pull-ups on LSI53C875A signals several signals in the LSI53C875A have internal pull-up resistors. ta b l e 3 . 1 describes the conditions that enable these pull-ups. i input, a standard input only signal. o output, a standard output driver (typically a totem pole output). i/o input and output (bidirectional). t/s 3-state, a bidirectional, 3-state input/output signal. s/t/s sustained 3-state, an active low 3-state signal owned and driven by one and only one agent at a time. table 3.1 LSI53C875A internal pull-ups signal name pull-up current conditions for pull-up irq/ 25 a pull-up enabled when the irq mode bit (bit 3 of dcntl (0x3b)) is cleared. gpio[1:0] 25 a pull-up enabled when bits [1:0] of general purpose pin control zero (gpcntl0) are not set. test_hsc/ 25 a pull-up enabled all the time. test_rst/ 25 a pull-up enabled all the time. trst,tck,tms,tdi 25 a pull-up enabled all the time.
3-4 signal descriptions 3.3 pci bus interface signals the pci bus interface signals section contains tables describing the signals for the following signal groups: system signals , address and data signals , interface control signals , arbitration signals , error reporting signals , and interrupt signal . 3.3.1 system signals ta b l e 3 . 2 describes the system signals. table 3.2 system signals name pqfp bga type strength description clk 145 a6 i n/a clock provides timing for all transactions on the pci bus and is an input to every pci device. all other pci signals are sampled on the rising edge of clk, and other timing parameters are defined with respect to this edge. clock can optionally serve as the scsi core clock, but this may effect fast scsi-2 (or faster) transfer rates. rst/ 144 b6 i n/a reset forcesthepcisequencerofeachdevicetoa known state. all t/s and s/t/s signals are forced to a high impedance state, and all internal logic is reset. the rst/ input is synchronized internally to the rising edge of clk. the clk input must be active while rst/ is active to properly reset the device.
pci bus interface signals 3-5 3.3.2 address and data signals ta b l e 3 . 3 describes address and data signals. table 3.3 address and data signals name pqfp bga type strength description ad[31:0] 150, 151, 153, 154, 156, 157, 159,160,3, 5, 6, 7, 9, 11?13, 28? 30, 32, 34? 36, 38, 40, 41, 43, 44, 46, 47, 49, 50 b5, c5, a4, b4, a3, c4, d4, a2, c2, e5, c1, d3, e4-e1, h5, j1, j2, h6, k2, j4, l1, l2, m1, n1, m3, l3, n3, l4, k5, n4 t/s 8 ma pci physical dword address and data are multiplexed on the same pci pins. a bus transaction consists of an address phase followed by one or more data phases. during the first clock of a transaction, ad[31:0] contain a 32-bit physical byte address. if the command is a dac, implying a 64-bit address, a second address phase is required. during the first phase, ad[31:0] will contain the lower 32 bits of the address followed by a second phase with ad[31:0] containing the upper 32 bits of the address. during subsequent clocks, ad[31:0] contain data. pci supports both read and write bursts. ad[7:0] define the least significant byte, and ad[31:24] define the most significant byte. c_be[3:0] 1, 15, 26, 39 a1, f3, h3, k4 t/s 8 ma pci bus command and byte enables are multiplexed on the same pci pins. during the address phase of a transaction, c_be[3:0]/ define the bus command. during the data phase, c_be[3:0]/ are used as byte enables. the byte enables determine which byte lanes carry meaningful data. c_be[0]/ applies to byte 0, and c_be[3]/ to byte 3. pa r 2 5 h 1 t / s 8 m a pci parity is the even parity bit that protects the ad[31:0] and c_be[3:0]/ lines. during the address phase, both the address and command bits are covered. during data phase, both data and byte enables are covered.
3-6 signal descriptions 3.3.3 interface control signals ta b l e 3 . 4 describes the interface control signals. table 3.4 interface control signals name pqfp bga type strength description frame/ 16 f2 s/t/s 8 ma pci cycle frame is driven by the current master to indicate the beginning and duration of an access. frame/ is asserted to indicate that a bus transaction is beginning. while frame/ is deasserted, either the transaction is in the final data phase or the bus is idle. trdy/ 19 g3 s/t/s 8 ma pci target ready indicates the target agent?s (selected device?s) ability to complete the current data phase of the transaction. trdy/ is used with irdy/. a data phase is completed on any clock when used with irdy/. a data phase is completed on any clock when both trdy/ and irdy/ are sampled asserted. during a read, trdy/ indicates that valid data is present on ad[31:0]. during a write, it indicates that the target is prepared to accept data. wait cycles are inserted until both irdy/ and trdy/ are asserted together. irdy/ 17 f1 s/t/s 8 ma pci initiator ready indicates the initiating agent?s (bus master?s) ability to complete the current data phase of the transaction. irdy/ is used with trdy/. a data phase is completed on any clock when both irdy/ and trdy/ are sampled asserted. during a write, irdy/ indicates that valid data is present on ad[31:0]. during a read, it indicates that the master is prepared to accept data. wait cycles are inserted until both irdy/ and trdy/ are asserted together. stop/ 22 g4 s/t/s 8 ma pci stop indicates that the selected target is requesting the master to stop the current transaction. devsel/ 20 g2 s/t/s 8 ma pci device select indicates that the driving device has decoded its address as the target of the current access. as an input, it indicates to a master whether any device on the bus has been selected. idsel 2 b1 i n/a initialization device select is used as a chip select in place of the upper 24 address lines during configuration read and write transactions.
pci bus interface signals 3-7 3.3.4 arbitration signals ta b l e 3 . 5 describes arbitration signals. 3.3.5 error reporting signals ta b l e 3 . 6 describes the error reporting signals. table 3.5 arbitration signals name pqfp bga type strength description req/ 148 e6 o 8 ma pci request indicates to the system arbiter that this agent desires use of the pci bus. this is a point-to-point signal. every master has its own req/ signal. gnt/ 147 d6 i n/a grant indicates to the agent that access to the pci bus has been granted. this is a point-to-point signal. every master has its own gnt/ signal. table 3.6 error reporting signals name pqfp bga type strength description perr/ 24 h2 s/t/ s 8mapci parity error may be pulsed active by an agent that detects a data parity error. perr/ can be used by any agent to signal data corruption. however, on detection of a perr/ pulse, the central resource may generate a nonmaskable interrupt to the host cpu, which often implies the system is unable to continue operation once error processing is complete. serr/ 143 e7 o 8 ma pci system error is an open drain output used to report address parity errors as well as critical errors other than parity.
3-8 signal descriptions 3.3.6 interrupt signal ta b l e 3 . 7 describes the interrupt signal. 3.4 scsi bus interface signals the scsi bus interface signals section contains tables describing the signals for the following signal groups: scsi bus interface signals , scsi signals ,and scsi control signals . 3.4.1 scsi bus interface signal ta b l e 3 . 8 describes the scsi bus interface signal. table 3.7 interrupt signal name pqfp bga type strength description irq/ 52 m5 o 8 ma pci interrupt request. this signal, when asserted low, indicates that an interrupting condition has occurred and that service is required from the host cpu. the output drive of this pin is open drain. 1. see register 0x4d, scsi test one (stest1) in chapter 4 for additional information on this signal. table 3.8 scsi bus interface signal name pqfp bga type strength description sclk 56 m6 i n/a scsi clock is used to derive all scsi-related timings. the speed of this clock is determined by the application?s requirements. in some applications, sclk may be sourced internally from the pci bus clock (clk). if sclk is internally sourced, then the sclk pin should be tied low.
scsi bus interface signals 3-9 3.4.2 scsi signals ta b l e 3 . 9 describes the scsi signals. 3.4.3 scsi control signals ta b l e 3 . 1 0 describes the scsi control signals. table 3.9 scsi signals name pqfp bga type strength description sd[15:0] 113, 115?17, 85?87, 89, 102, 103, 105?108, 110, 111 d13, e10, c13, d11, j9, l13, k11, j10, g10, g9, f13, f11?9, e12, e11 i/o 48 ma scsi scsi data. sdp[1:0] 112, 101 f8, g13 i/o 48 ma scsi scsi parity. table 3.10 scsi control signals name pqfp bga type strength description scd 92 j12 i/o 48 ma scsi phase line, command/data sio 90 k13 i/o 48 ma scsi phase line, input/output. smsg 95 h11 i/o 48 ma scsi phase line, message. sreq 91 j11 i/o 48 ma data handshake line from target device. sack 97 h13 i/o 48 ma data handshake signal from the initiator device. sbsy 98 h9 i/o 48 ma scsi bus arbitration signal, busy. satn 100 g12 i/o 48 ma scsi attention, the initiator is requesting a message out phase. srst 96 h12 i/o 48 ma scsi bus reset. ssel 94 h10 i/o 48 ma scsi bus arbitration signal, select device.
3-10 signal descriptions 3.5 gpio signals ta b l e 3 . 1 1 describes the scsi gpio signals. table 3.11 gpio signals name pqfp bga type strength description gpio0_fetch/ 53 n5 i/o 8 ma scsi general purpose i/o pin. optionally, when driven low, indicates that the next bus request will be for an opcode fetch. this pin is programmable at power-up through the mad7 pin to serve as the data signal for the serial eeprom interface. this signal can also be programmedtobedrivenlowwhenthe LSI53C875A is active on the scsi bus. gpio1_master/ 54 k6 i/o 8 ma scsi general purpose i/o pin. optionally, when driven low, indicates that the LSI53C875A is bus master. this pin is programmable at power-up through the mad7 pin to serve as the clock signal for the serial eeprom interface. gpio2 68 j8 i/o 8 ma scsi general purpose i/o pin. this pin powers up as an input. gpio3 70 m9 i/o 8 ma scsi general purpose i/o pin. this pin powers up as an input. gpio4 71 l9 i/o 8 ma scsi general purpose i/o pin. gpio4 powers up as an output. (this pin may be used as the enable line for vpp, the 12 v power supply to the external flash memory interface.)
rom flash and memory interface signals 3-11 3.6 rom flash and memory interface signals ta b l e 3 . 1 2 describes the rom flash and memory interface signals. table 3.12 rom flash and memory interface signals name pqfp bga type strength description mwe/ 139 c7 o 4 ma memory write enable. thispinisusedasawrite enable signal to an external flash memory. mce/ 141 a7 o 4 ma memory chip enable. thispinisusedasachip enable signal to an external eeprom or flash memory device. moe/ 140 b7 o 4 ma memory output enable. thispinisusedasan output enable signal to an external eeprom or flash memory during read operations. it is also used to test the connectivity of the LSI53C875A signals in test mode. mac/_ testout 77 l10 o 16 ma memory access control. this pin can be programmed to indicate local or system memory accessed (non-pci applications). it is also used to test the connectivity of the LSI53C875A signals in test mode. mas0/ 137 a8 o 4 ma memory address strobe 0 . this pin is used to latch in the least significant address byte (bits [7:0]) of an external eeprom or flash memory. since the LSI53C875A moves addresses eight bits at a time, this pin connects to the clock of an external bank of flip-flops which are used to assemble up to a 20-bit address for the external memory. mas1/ 136 b8 o 4 ma memory address strobe 1. this pin is used to latch in the most significant address byte (bits [15:8]) of an external eeprom or flash memory. since the LSI53C875A moves addresses eight bits at a time, this pin connects to the clock of an external bank of flip-flops which assemble up to a 20-bit address for the external memory.
3-12 signal descriptions 3.7 test interface signals ta b l e 3 . 1 3 describes test interface signals. mad[7:0] 59?62, 64?67 l7, m7, n7, k7, m8, n8, l8, k8 i/o 4 ma memory address/data bus. this bus is used in conjunction with the memory address strobe pins and external address latches to assemble up to a 20-bit address for an external eeprom or flash memory. this bus will put out the least significant byte first and finishes with the most significant bits. it is also used to write data to a flash memory or read data into the chip from external eeprom/ flash memory. these pins have static pull-downs. table 3.12 rom flash and memory interface signals (cont.) name pqfp bga type strength description table 3.13 test interface signals name pqfp bga type strength description test_hsc/ 126 a11 i n/a test halt scsi clock. for lsi logic test purposes only. pulled high internally. this signal can also cause a full chip reset. tck 130 a10 i n/a test clock. this pin provides the clock for the jtag test logic. tms 57 n6 i n/a test mode select . the signal received at tms is decoded by the tap controller to control jtag test operations. this pin has a static pull-down. tdi 142 d7 i n/a test data in. serial test instructions are received by the jtag test logic at this pin. this pin has a static pull-down. test_rst/ 127 c10 i n/a test reset. for test purposes only. pulled high internally. tdo 58 j6 o 4 ma test data out. this pin is the serial output for test instructions and data from the jtag test logic. trst/ 131 c9 i n/a test reset . this pin provides a reset for jtag test logic. pulled high internally.
power and ground signals 3-13 3.8 power and ground signals ta b l e 3 . 1 4 describes the power and ground signals. table 3.14 power and ground signals name pqfp bga type strength description vss_i/o 4, 10, 14, 18, 23, 27, 31, 37, 42, 48, 69, 79, 88, 93, 99, 104, 109, 114, 123, 133, 152, 158 a9,b11,d12, e13, f12, g11, j13, k10, k12, n9 g n/a ground for pci bus drivers/receivers, scsi bus drivers/receivers, local memory interface drivers, and other i/o pins. vdd_i/o 8, 21, 33, 45, 63, 74, 84, 118, 128, 138, 155 b10, c12, d2, d5, e8, g1, j5, j7, k1, l11, m10 p n/a power for pci bus drivers/receivers, scsi bus drivers/receivers, local memory interface drivers/receivers, and other i/o pins. vdd_core 51, 83, 149 a5, l5, l12 p n/a power for core logic. vss_core 55, 80, 146 c6, l6, n12 g n/a ground for core logic. vdda 129 d9 p n/a power for analog cells (clock quadrupler and diffsense logic). vssa 132 b9 g n/a ground for analog cells (clock quadrupler and diffsense logic). nc 72, 73, 75, 76, 78, 81, 82, 119?122, 124, 125, 134, 135 a12, a13, b2, b3, b12, b13, c3, c8, c11, d1, d8, d10, e9, f4-6, g5, h4, h8, j3, k3, k9, m2, m4, m11-13, n2, n10, n11, n13 n/a n/a these pins have no internal connection. note: the i/o driver pad rows and digital core have isolated power supplies as indicated by the ?i/o? and ?core? extensions on their respective v ss and v dd names. these power and ground pins should be connected directly to the primary power and ground planes of the circuit board. bypass capacitors of 0.01 f should be applied between adjacent v ss and v dd pairs wherever possible. do not connect bypass capacitors between v ss and v dd pairs that cross power and ground bus boundaries.
3-14 signal descriptions 3.9 mad bus programming the mad[7:0] pins, in addition to serving as the address/data bus for the local memory interface, also are used to program power-up options for the chip. a particular option is programmed allowing the internal pull-down current sink to pull the pin low at reset or by connecting a 4.7 k ? resistor between the appropriate mad[x] pin and v ss .the pull-down resistors require that hc or hct external components are used for the memory interface. the mad[7:0] pins are sensed by internal circuitry three pci clock cycles after rst/ is deasserted. ? mad[7] serial eeprom programmable option. when allowed to be pulled low by the internal pull-down current sink, the automatic data download is enabled. when pulled high by an external resistor, the automatic data download is disabled. please see section 2.4, ?serial eeprom interface,? in chapter 2 and subsystem id and subsystem vendor id registers in chapter 4 for additional information. ? mad[6:4] reserved and may be left floating. ? the mad[3:1] pins are used to set the size of the external expansion rom device attached. encoding for these pins are listed in ta b l e 3 . 1 5 (?0? indicates a pull-down resistor is attached, ?1? indicates a pull-up resistor is attached). table 3.15 decode of mad pins mad[3:1] available memory space 000 16 kbyte 001 32 kbyte 010 64 kbyte 011 128 kbyte 100 256 kbyte 101 512 kbyte 110 1024 kbyte 111 no external memory present
mad bus programming 3-15 ? the mad[0] pin is the slow rom pin. when pulled up, it enables two extra cycles of data access time to allow use of slower memory devices. ? all mad pins have internal pull-down resistors.
3-16 signal descriptions
LSI53C875A pci to ultra scsi controller 4-1 chapter 4 registers this chapter describes all LSI53C875A registers and is divided into the following sections: ? section 4.1 ?pci configuration registers? ? section 4.2 ?scsi registers? ? section 4.3 ?64-bit scripts selectors? ? section 4.4 ?phase mismatch jump registers? in the register descriptions, the term ?set? is used to refer to bits that are programmed to a binary one. similarly, the term ?cleared? is used to refer to bits that are programmed to a binary zero. write any bits marked as reserved to zero; mask all information read from them. reserved bit functions may change at any time. unless otherwise indicated, all bits in registers are active high, that is, the feature is enabled by setting the bit. the bottom row of every register diagram shows the default register values, which are enabled after the chip is powered on or reset. reserved registers and bits are shaded in the register tables. 4.1 pci configuration registers the pci configuration registers are accessed by performing a configuration read/write to the device with its idsel pin asserted and the appropriate value in ad[10:8] during the address phase of the transaction. the LSI53C875A responds to a binary value of 000b. ta b l e 4 . 1 describes the pci configuration registers all pci-compliant devices must support the vendor id , device id , command ,and status registers. support of other pci-compliant registers is optional. in the LSI53C875A, registers that are not supported are not writable and return all zeros when read. only those registers and
4-2 registers bits that are currently supported by the LSI53C875A are described in this chapter. reserved bits should not be accessed . registers: 0x00?0x01 vendor id read only vid vendor id [15:0] this 16-bit register identifies the manufacturer of the device. the vendor id is 0x1000. table 4.1 pci configuration register map 31 16 15 0 device id vendor id 0x00 status command 0x04 class code revision id (rev id) 0x08 not supported header type latency timer cache line size 0x0c base address register zero (i/o) 0x10 base address register one (memory) bits [31:0] 0x14 base address register two (scripts ram) 0x18 not supported 0x1c not supported 0x20 not supported 0x24 reserved 0x28 subsystem id subsystem vendor id 0x2c expansion rom base address 0x30 reserved capabilities pointer 0x34 reserved 0x38 max_lat min_gnt interrupt pin interrupt line 0x3c power management capabilities (pmc) next item pointer capability id 0x40 data bridge support exten- sions (pmcsr_bse) power management control/status (pmcsr) 0x44 not supported 0x48 15 0 vid 0001000000000000
pci configuration registers 4-3 registers: 0x02?0x03 device id read only did device id [15:0] this 16-bit register identifies the particular device. the LSI53C875A device id is 0x0013. registers: 0x04?0x05 command read/write the command register provides coarse control over a device?s ability to generate and respond to pci cycles. when a zero is written to this register, the LSI53C875A is logically disconnected from the pci bus for all accesses except configuration accesses. r reserved [15:9] se serr/ enable 8 this bit enables the serr/ driver. serr/ is disabled when this bit is cleared. the default value of this bit is zero. this bit and bit 6 must be set to report address parity errors. r reserved 7 eper enable parity error response 6 this bit allows the LSI53C875A to detect parity errors on the pci bus and report these errors to the system. only data parity checking is enabled and disabled with this bit. the LSI53C875A always generates parity for the pci bus. 15 0 did 0000000000010011 15 9876543 2 1 0 rse r eper rwie rebmemseis x x x x x x x0 x0 x0 x0 00
4-4 registers r reserved 5 wie write and invalidate enable 4 this bit allows the LSI53C875A to generate write and invalidate commands on the pci bus. the wie bit in the dma control (dcntl) register must also be set for the device to generate write and invalidate commands. r reserved 3 ebm enable bus mastering 2 this bit controls the ability of the LSI53C875A to act as a master on the pci bus. a value of zero disables this device from generating pci bus master accesses. a value of one allows the LSI53C875A to behave as a bus master. the device must be a bus master in order to fetch scripts instructions and transfer data. ems enable memory space 1 this bit controls the ability of the LSI53C875A to respond to memory space accesses. a value of zero disables the device response. a value of one allows the LSI53C875A to respond to memory space accesses at the address range specified by base address register one (mem- ory) and base address register two (scripts ram) registers in the pci configuration space. eis enable i/o space 0 this bit controls the LSI53C875A response to i/o space accesses. a value of zero disables the device response. a value of one allows the LSI53C875A to respond to i/o space accesses at the address range specified by the base address register zero (i/o) register in the pci configuration space.
pci configuration registers 4-5 registers: 0x06?0x07 status read/write reads to this register behave normally. writes are slightly different in that bits can be cleared, but not set. a bit is cleared whenever the register is written, and the data in the corresponding bit location is a one. for instance, to clear bit 15 and not affect any other bits, write the value 0x8000 to the register. dpe detected parity error (from slave) 15 this bit is set by the LSI53C875A whenever it detects a data parity error, even if data parity error handling is disabled. sse signaled system error 14 this bit is set whenever the device asserts the serr/ signal. rma received master abort (from master) 13 a master device should set this bit whenever its transaction (except for special cycle) is terminated with master abort. rta received target abort (from master) 12 a master device should set this bit whenever its transaction is terminated by target abort. r reserved 11 dt[1:0] devsel/ timing [10:9] these bits encode the timing of devsel/. these are encoded as: 15 14 13 12 11 10 9 8 7 5 4 3 0 dpe sse rma rta r dt[1:0] dpr rnc r 0000 x010 x x x1 x x x x 0b00 fast 0b01 medium 0b10 slow 0b11 reserved
4-6 registers these bits are read only and should indicate the slowest time that a device asserts devsel/ for any bus command except configuration read and configuration write. the LSI53C875A supports a value of 0b01. dpr data parity error reported 8 this bit is set when all of the following conditions are met: ? the bus agent asserted perr/ itself or observed perr/ asserted. ? the agent setting this bit acted as the bus master for the operation in which the error occurred. ? the parity error response bit in the command register is set. r reserved [7:5] nc new capabilities 4 this bit is set to indicate a list of extended capabilities such as pci power management. this bit is read only. r reserved [3:0] register: 0x08 revision id (rev id) read only rid revision id [7:0] this register contains the current revision level of the device. 7 0 rid xxxxxxxx
pci configuration registers 4-7 registers: 0x09?0x0b class code read only cc class code [23:0] this 24-bit register is used to identify the generic function of the device. the upper byte of this register is a base class code, the middle byte is a subclass code, and the lower byte identifies a specific register level programming interface. the value of this register is 0x010000, which identifies a scsi controller. register: 0x0c cachelinesize read/write cls cache line size [7:0] this register specifies the system cache line size in units of 32-bit words. the value in this register is used by the device to determine whether to use write and invalidate or write commands for performing write cycles, and whether to use read, read line, or read multiple commands for performing read cycles as a bus master. devices participating in the caching protocol use this field to know when to retry burst accesses at cache line boundaries. these devices can ignore the pci cache support lines (sdone and sb0/) when this register is cleared to 0. if this register is programmed to a number which is not a power of 2, the device will not use pci performance commands to perform data transfers. 23 0 cc 000000010000000000000000 7 0 cls 00000000
4-8 registers register: 0x0d latency timer read/write lt latency timer [7:0] the latency timer register specifies, in units of pci bus clocks, the value of the latency timer for this pci bus master. the LSI53C875A supports this timer. all eight bits are writable, allowing latency values of 0?255 pci clocks. use the following equation to calculate an optimum latency value for the LSI53C875A. latency = 2 + (burst size x (typical wait states + 1)) values greater than optimum are also acceptable. register: 0x0e header type read only ht header type [7:0] this register identifies the layout of bytes 0x10 through 0x3f in configuration space and also whether or not the device contains multiple functions. since the LSI53C875A is not a multifunction controller the value of this register is 0x00. register: 0x0f not supported 7 0 lt 00000000 7 0 ht 00000000
pci configuration registers 4-9 registers: 0x10?0x13 base address register zero (i/o) read/write bar0 base address register zero - i/o [31:0] this base address register is used to map the operating register set into i/o space. the LSI53C875A requires 256 bytes of i/o space for this base address register. it has bit zero hardwired to one. bit 1 is reserved and returns a zero on all reads, and the other bits are used to map the device into i/o space. for detailed information on the operation of this register, refer to the pci 2.2 specification. registers: 0x14?0x17 base address register one (memory) read/write bar1 base address register one [31:0] this base address register maps scsi operating registers into memory space. this device requires 1024 bytes of address space for this base register. this register has bits [9:0] hardwired to 0b0000000000. the default value of this register is 0x00000000. for detailed information on the operation of this register, refer to the pci 2.2 specification. 31 0 bar0 00000000000000000000000000000001 31 0 bar1 00000000000000000000000000000000
4-10 registers registers: 0x18?0x1b base address register two (scripts ram) read/write bar2 base address register two [31:0] this base register is used to map the scripts ram into memory space. the default value of this register is 0x00000000. the LSI53C875A points to 4096 bytes of address space with this register. this register has bits [11:0] hardwired to 0b000000000000. for detailed information on the operation of this register, refer to the pci 2.2 specification. registers: 0x1c?0x27 not supported registers: 0x28?0x2b reserved registers: 0x2c?0x2d subsystem vendor id read only svid subsystem vendor id [15:0] this 16-bit register is used to uniquely identify the vendor manufacturing the add-in board or subsystem where this pci device resides. it provides a mechanism for an add-in card vendor to distinguish its cards from another vendor?s cards, even if the cards have the same pci 31 0 bar2 00000000000000000000000000000000 15 0 svid if mad[7] high default 0001000000000000 if mad[7] low see description default xxxxxxxxxxxxxxxx
pci configuration registers 4-11 controller installed on them (and therefore the same vendor id and device id). if the external serial eeprom interface is enabled (mad[7] low), this register is automatically loaded at power-up from the external serial eeprom and will contain the value downloaded from the serial eeprom or a value of 0x0000 if the download fails. if the external serial eeprom interface is disabled (mad[7] high), this register returns a value of 0x1000 (lsi logic vendor id). the 16-bit value that should be stored in the external serial eeprom for this register is the vendor?s pci vendor id and must be obtained from the pci special interest group (sig). please see section 2.4, ?serial eeprom interface,? in chapter 2 for more information on downloading a value for this register. registers: 0x2e?0x2f subsystem id read only sid subsystem id [15:0] this 16-bit register is used to uniquely identify the add-in board or subsystem where this pci device resides. it provides a mechanism for an add-in card vendor to distinguish its cards from one another even if the cards have the same pci controller installed on them (and therefore the same vendor id and device id). if the external serial eeprom interface is enabled (mad[7] is low), this register is automatically loaded at power-up from the external serial eeprom and will contain the value downloaded from the serial eeprom or a value of 0x0000 if the download fails. if the external serial eeprom is disabled (mad[7] pulled high), the register returns a value of 0x1000. the 16-bit 15 0 sid if mad[7] high default 0001000000000000 if mad[7] low see description default xxxxxxxxxxxxxxxx
4-12 registers value that should be stored in the external serial eeprom is vendor specific. please see the section 2.4 ?serial eeprom interface? in chapter 2 for additional information on downloading a value for this register. registers: 0x30?0x33 expansion rom base address read/write erba expansion rom base address [31:0] this four-byte register handles the base address and size information for the expansion rom. it functions exactly like the base address register zero (i/o) and one (memory) registers, except that the encoding of the bits is different. the upper 21 bits correspond to the upper 21 bits of the expansion rom base address. theexpansionromenablebit,bit0,istheonlybit defined in this register. this bit is used to control whether or not the device accepts accesses to its expansion rom. when the bit is set, address decoding is enabled, and a device is used with or without an expansion rom depending on the system configuration. to access the external memory interface, also set the memory space bit in the command register. the host system detects the size of the external memory by first writing the expansion rom base address register with all ones and then reading back the register. the LSI53C875A responds with zeros in all don?t care locations. the ones in the remaining bits represent the binary version of the external memory size. for example, to indicate an external memory size of 32 kbytes, this register, when written with ones and read back, returns ones in the upper 17 bits. the size of the external memory is set through mad[3:1]. please see the section on mad bus programming for the possible size encodings available. 31 0 erba[31:0] 00000000000000000000000000000000
pci configuration registers 4-13 register: 0x34 capabilities pointer read only cp capabilities pointer [7:0] this register indicates that the first extended capability register is located at offset 0x40 in the pci configuration. registers: 0x35?0x3b reserved register: 0x3c interrupt line read/write il interrupt line [7:0] this register is used to communicate interrupt line routing information. post software writes the routing information into this register as it configures the system. the value in this register tells which input of the system interrupt controller(s) the device?s interrupt pin is connected to. values in this register are specified by system architecture. 7 0 cp 01000000 7 0 il 00000000
4-14 registers register: 0x3d interrupt pin read only ip interrupt pin [7:0] this register indicates which interrupt pin the device uses. its value is set to 0x01 for the inta/ signal. register: 0x3e min_gnt read only mg min_gnt [7:0] this register is used to specify the desired settings for latency timer values. min_gnt is used to specify how long a burst period the device needs. the value specified in this register is in units of 0.25 microseconds. the LSI53C875A sets this register to 0x11. register: 0x3f max_lat read only ml max_lat [7:0] this register is used to specify the desired settings for latency timer values. max_lat is used to specify how often the device needs to gain access to the pci bus. the value specified in this register is in units of 0.25 microseconds. the LSI53C875A sets this register to 0x40. 7 0 ip 00000001 7 0 mg 00010001 7 0 ml 01000000
pci configuration registers 4-15 register: 0x40 capability id read only cid cap_id [7:0] this register indicates the type of data structure currently being used. it is set to 0x01, indicating the power management data structure. register: 0x41 next item pointer read only nip next_item_ptr [7:0] bits [7:0] contain the offset location of the next item in the controller?s capabilities list. the LSI53C875A has these bits set to zero indicating no further extended capabilities registers exist. registers: 0x42?0x43 power management capabilities (pmc) read only pmes pme_support [15:11] bits [15:11] define the power management states in which the LSI53C875A will assert the pme pin. these bits are all set to zero because the LSI53C875A does not provide a pme signal. 7 0 cid 00000001 7 0 nip 00000000 15 11 10 9 8 6 5 4 3 2 0 pmes d2s d1s r dsi aps pmec ver[2:0] 00000 1 1 x x x00 0 010
4-16 registers d2s d2_support 10 the LSI53C875A sets this bit to indicate support for power management state d2. d1s d1_support 9 the LSI53C875A sets this bit to indicate support for power management state d1. r reserved [8:6] dsi device specific initialization 5 this bit is cleared to indicate that the LSI53C875A requires no special initialization before the generic class device driver is able to use it. aps auxiliary power source 4 because the LSI53C875A does not provide a pme signal, this bit is cleared, indicating that no auxiliary power source is required to support the pme signal in the d3cold power management state. pmec pme clock 3 bit 3 is cleared because the LSI53C875A does not provide a pme pin. ver[2:0] version [2:0] these three bits are set to 010 to indicate that the LSI53C875A complies with revision 1.1 of the pci power management interface specification. registers: 0x44?0x45 power management control/status (pmcsr) read/write pst pme status 15 the LSI53C875A always returns a zero for this bit, indicating that pme signal generation is not supported from d3cold. 15 14 13 12 9 8 7 2 1 0 pst dscl dslt pen rpws[1:0] 00000000 x x x x x x00
pci configuration registers 4-17 dscl data_scale [14:13] the LSI53C875A does not support the data register. therefore, these two bits are always cleared. dslt data_select [12:9] the LSI53C875A does not support the data register. therefore, these four bits are always cleared. pen pme_enable 8 the LSI53C875A always returns a zero for this bit to indicate that pme assertion is disabled. r reserved [7:2] pws[1:0] power state [1:0] bits [1:0] are used to determine the current power state of the LSI53C875A. they are used to place the LSI53C875A in a new power state. power states are defined as: see section 2.5, ?power management,? in chapter 2 for descriptions of the power management states. register: 0x46 bridge support extensions (pmcsr_bse) read only bse bridge support extensions [7:0] this register indicates pci bridge specific functionality. the LSI53C875A does not support extensions and always returns 0x00. 0b00 d0 0b01 d1 0b10 d2 0b11 d3hot 7 0 bse 00000000
4-18 registers register: 0x47 data read only data data [7:0] this register provides an optional mechanism for the function to report state-dependent operating data. the LSI53C875A does not use this register and always returns 0x00. 4.2 scsi registers the control registers for the scsi core are directly accessible from the pci bus using memory or i/o mapping. the address map of the scsi registers is shown in ta b l e 4 . 2 . note: the only registers that the host cpu can access while the LSI53C875A is executing scripts are the interrupt status zero (istat0) , interrupt status one (istat1) and mailbox zero (mbox0) , mailbox one (mbox1) registers; attempts to access other registers interfere with the operation of the chip. however, all operating registers are accessible with scripts. all read data is synchronized and stable when presented to the pci bus. 7 0 data 00000000
scsi registers 4-19 table 4.2 scsi register address map 31 16 15 0 scntl3 scntl2 scntl1 scntl0 0x00 gpreg0 sdid sxfer scid 0x04 sbcl ssid socl sfbr 0x08 sstat2 sstat1 sstat0 dstat 0x0c dsa 0x10 mbox1 mbox0 istat1 istat0 0x14 ctest3 ctest2 ctest1 ctest0 0x18 temp 0x1c ctest6 ctest5 ctest4 dfifo 0x20 dcmd dbc 0x24 dnad 0x28 dsp 0x2c dsps 0x30 scratch a 0x34 dcntl sbr dien dmode 0x38 adder 0x3c sist1 sist0 sien1 sien0 0x40 gpcntl0 macntl swide slpar 0x44 respid1 respid0 stime1 stime0 0x48 stest3 stest2 stest1 stest0 0x4c reserved stest4 sidl 0x50 ccntl1 ccntl0 sodl 0x54 reserved reserved sbdl 0x58 scratch b 0x5c scratch c?scratch r 0x60?0x9f mmrs 0xa0 mmws 0xa4 sfs 0xa8 drs 0xac sbms 0xb0 dbms 0xb4 dnad64 0xb8 reserved 0xbc pmjad1 0xc0 pmjad2 0xc4 rbc 0xc8 ua 0xcc esa 0xd0 ia 0xd4 reserved sbc 0xd8 csbc 0xdc reserved 0xe0?0xff
4-20 registers register: 0x00 scsi control zero (scntl0) read/write arb[1:0] arbitration mode bits 1 and 0 [7:6] simple arbitration 1. the LSI53C875A waits for a bus free condition to occur. 2. it asserts sbsy/ and its scsi id (contained in the scsi chip id (scid) register) onto the scsi bus. if the ssel/ signal is asserted by another scsi device, the LSI53C875A deasserts sbsy/, deasserts its id and sets the lost arbitration bit (bit 3) in the scsi status zero (sstat0) register. 3. after an arbitration delay, the cpu should read the scsi bus data lines (sbdl) register to check if a higher priority scsi id is present. if no higher priority id bit is set, and the lost arbitration bit is not set, the LSI53C875A wins arbitration. 4. once the LSI53C875A wins arbitration, ssel/ must be asserted using the scsi output control latch (socl) for a bus clear plus a bus settle delay (1.2 s) before a low level selection is performed. 76543210 arb[1:0] start watn epc raaptrg 11000 x00 arb1 arb0 arbitration mode 0 0 simple arbitration 01 reserved 10 reserved 1 1 full arbitration, selection/reselection
scsi registers 4-21 full arbitration, selection/reselection 1. the LSI53C875A waits for a bus free condition. 2. it asserts sbsy/ and its scsi id (the highest priority id stored in the scsi chip id (scid) register) onto the scsi bus. 3. if the ssel/ signal is asserted by another scsi device or if the LSI53C875A detects a higher priority id, the LSI53C875A deasserts sbsy, deasserts its id, and waits until the next bus free state to try arbitration again. 4. the LSI53C875A repeats arbitration until it wins control of the scsi bus. when it wins, the won arbitration bit is set in the scsi status zero (sstat0) register, bit 2. 5. the LSI53C875A performs selection by asserting the following onto the scsi bus: ssel/, the target?s id (stored in the scsi destination id (sdid) register), and the LSI53C875A?s id (stored in the scsi chip id (scid) register). 6. after a selection is complete, the function complete bit is set in the scsi interrupt status zero (sist0) register, bit 6. 7. if a selection time-out occurs, the selection time-out bit is set in the scsi interrupt status one (sist1) register, bit 2. start start sequence 5 when this bit is set, the LSI53C875A starts the arbitration sequence indicated by the arbitration mode bits. the start sequence bit is accessed directly in low level mode; during scsi scripts operations, this bit is controlled by the scripts processor. do not start an arbitration sequence if the connected (con) bit in the scsi control one (scntl1) register, bit 4, indicates that the LSI53C875A is already connected to the scsi bus. this bit is automatically cleared when the arbitration sequence is complete. if a sequence is aborted, check bit 4 in the scntl1 register to verify that the LSI53C875A is not connected to the scsi bus.
4-22 registers watn select with satn/ on a start sequence 4 when this bit is set and the LSI53C875A is in the initiator mode, the satn/ signal is asserted during selection of a scsi target device. this is to inform the target that the LSI53C875A has a message to send. if a selection time-out occurs while attempting to select a target device, satn/ is deasserted at the same time ssel/ is deasserted. when this bit is cleared, the satn/ signal is not asserted during selection. when executing scsi scripts, this bit is controlled by the scripts processor, but manual setting is possible in low level mode. epc enableparitychecking 3 when this bit is set, the scsi data bus is checked for odd parity when data is received from the scsi bus in either the initiator or target mode. if a parity error is detected, bit 0 of the scsi interrupt status zero (sist0) register is set and an interrupt may be generated. if the LSI53C875A is operating in the initiator mode and a parity error is detected, assertion of satn/ is optional, but the transfer continues until the target changes phase. when this bit is cleared, parity errors are not reported. r reserved 2 aap assert satn/ on parity error 1 when this bit is set, the LSI53C875A automatically asserts the satn/ signal upon detection of a parity error. satn/isonlyassertedintheinitiatormode.thesatn/ signal is asserted before deasserting sack/ during the byte transfer with the parity error. also set the enable parity checking bit for the LSI53C875A to assert satn/ in this manner. a parity error is detected on data received from the scsi bus. if the assert satn/ on parity error bit is cleared or the enable parity checking bit is cleared, satn/ is not automatically asserted on the scsi bus when a parity error is received. trg target mode 0 this bit determines the default operating mode of the LSI53C875A. the user must manually set the target or initiator mode. this is done using the scripts language
scsi registers 4-23 ( set target or clear target ). when this bit is set, the chip is a target device by default. when this bit is cleared, the LSI53C875A is an initiator device by default. caution: writing this bit while not connected may cause the loss of a selection or reselection due to the changing of target or initiator modes. register: 0x01 scsi control one (scntl1) read/write exc extra clock cycle of data setup 7 when this bit is set, an extra clock period of data setup is added to each scsi data transfer. the extra data setup time can provide additional system design margin, though it affects the scsi transfer rates. clearing this bit disables the extra clock cycle of data setup time. setting this bit only affects scsi send operations. adb assert scsi data bus 6 when this bit is set, the LSI53C875A drives the contents of the scsi output data latch (sodl) register onto the scsi data bus. when the LSI53C875A is an initiator, the scsi i/o signal must be inactive to assert the sodl contents onto the scsi bus. when the LSI53C875A is a target, the scsi i/o signal must be active to assert the sodl contents onto the scsi bus. the contents of the scsi output data latch (sodl) register can be asserted at any time, even before the LSI53C875A is connected to the scsi bus. clear this bit when executing scsi scripts. it is normally used only for diagnostic testing or operation in low level mode. dhp disable halt on parity error or atn (target only) 5 the dhp bit is only defined for target mode. when this bit is cleared, the LSI53C875A halts the scsi data transfer when a parity error is detected or when the satn/ signal is asserted. if satn/ or a parity error is received in the middle of a data transfer, the LSI53C875A 76543210 exc adb dhp con rst aesp iarb sst 00000000
4-24 registers may transfer up to three additional bytes before halting to synchronize between internal core cells. during synchronous operation, the LSI53C875A transfers data until there are no outstanding synchronous offsets. if the LSI53C875A is receiving data, any data residing in the dma fifo is sent to memory before halting. when this bit is set, the LSI53C875A does not halt the scsi transfer when satn/ or a parity error is received. con connected 4 this bit is automatically set any time the LSI53C875A is connected to the scsi bus as an initiator or as a target. it is set after the LSI53C875A successfully completes arbitration or when it has responded to a bus initiated selection or reselection. this bit is also set after the chip wins simple arbitration when operating in low level mode. when this bit is cleared, the LSI53C875A is not connected to the scsi bus. the cpu can force a connected or disconnected condition by setting or clearing this bit. this feature is used primarily during loopback mode. rst assert scsi rst/ signal 3 setting this bit asserts the srst/ signal. the srst/ output remains asserted until this bit is cleared. the 25 = s minimum assertion time defined in the scsi specification must be timed out by the controlling microprocessor or a scripts loop. aesp assert even scsi parity (force bad parity) 2 when this bit is set, the LSI53C875A asserts even parity. it forces a scsi parity error on each byte sent to the scsi bus from the chip. if parity checking is enabled, then the LSI53C875A checks data received for odd parity. this bit is used for diagnostic testing and is cleared for normal operation. it is useful to generate parity errors to test error handling functions. iarb immediate arbitration 1 setting this bit causes the scsi core to immediately begin arbitration once a bus free phase is detected following an expected scsi disconnect. this bit is useful for multithreaded applications. the arb[1:0] bits in the
scsi registers 4-25 scsi control zero (scntl0) register are set for full arbitration and selection before setting this bit. arbitration is retried until won. at that point, the LSI53C875A holds sbsy and ssel asserted, and waits for a select or reselect sequence. the immediate arbitration bit is cleared automatically when the selection or reselection sequence is completed, or times out. an unexpected disconnect condition clears iarb with it attempting arbitration. see the scsi disconnect unexpected bit ( scsi control two (scntl2) ,bit7)for more information on expected versus unexpected disconnects. it is possible to abort an immediate arbitration sequence. first, set the abort bit in the interrupt status zero (istat0) register. then one of two things eventually happens: ? the won arbitration bit ( scsi status zero (sstat0) , bit 2) will be set. in this case, the immediate arbitration bit needs to be cleared. this completes the abort sequence and disconnects the chip from the scsi bus. if it is not acceptable to go to bus free phase immediately following the arbitration phase, it is possible to perform a low level selection instead. ? the abort completes because the LSI53C875A loses arbitration. this is detected by the clearing of the immediate arbitration bit. do not use the lost arbitration bit ( scsi status zero (sstat0) ,bit3)to detect this condition. in this case take no further action. sst start scsi transfer 0 this bit is automatically set during scripts execution and should not be used. it causes the scsi core to begin a scsi transfer, including sreq/ and sack/ handshaking. the determination of whether the transfer is a send or receive is made according to the value written to the i/o bit in scsi output control latch (socl) . this bit is self-clearing. do not set it for low level operation.
4-26 registers caution: writing to this register while not connected may cause the loss of a selection/reselection by clearing the connected bit. register: 0x02 scsi control two (scntl2) read/write sdu scsi disconnect unexpected 7 this bit is valid in the initiator mode only. when this bit is set, the scsi core is not expecting the scsi bus to enter the bus free phase. if it does, an unexpected disconnect error is generated (see the unexpected disconnect bit in the scsi interrupt status zero (sist0) register, bit 2). during normal scripts mode operation, this bit is set automatically whenever the scsi core is reselected, or successfully selects another scsi device. the sdu bit should be cleared with a register write (move 0x00 to scntl2) before the scsi core expects a disconnect to occur, normally prior to sending an abort, abort tag, bus device reset, clear queue or release recovery message, or before deasserting sack/ after receiving a disconnect command or command complete message. chm chained mode 6 this bit determines whether or not the scsi core is programmed for chained scsi mode. this bit is automatically set by the chained block move (chmov) scripts instruction and is automatically cleared by the block move scripts instruction (move). chained mode is primarily used to transfer consecutive wide data blocks. using chained mode facilitates partial receive transfers and allows correct partial send behavior. when this bit is set and a data transfer ends on an odd byte boundary, the LSI53C875A stores the last byte in the scsi wide residue (swide) register during a receive operation, or in the scsi output data latch (sodl) register during a send operation. this byte is 76543210 sdu chm slpmd slphben wss vue0 vue1 wsr 00000000
scsi registers 4-27 combined with the first byte from the subsequent transfer so that a wide transfer is completed. slpmd slpar mode 5 if this bit is cleared, the scsi longitudinal parity (slpar) register functions as a byte-wide longitudinal parity register. if this bit is set, the slpar functions as a word-wide longitudinal parity function. the high or low byte of the slpar word is accessible through the slpar register. which byte is accessible is controlled by the slphben bit. slphben slpar high byte enable 4 if this bit is cleared, the low byte of the slpar word is accessible through the scsi longitudinal parity (slpar) register. if this bit is set, the high byte of the slpar word is present in the slpar register. wss wide scsi send 3 when read, this bit returns the value of the wide scsi send (wss) flag. asserting this bit clears the wss flag. this clearing function is self-clearing. when the wss flag is high following a wide scsi send operation, the scsi core is holding a byte of ?chain? data in the scsi output data latch (sodl) register. this data becomes the first low-order byte sent when married with a high-order byte during a subsequent data send transfer. performing a scsi receive operation clears this bit. also, performing any nonwide transfer clears this bit. vue0 vendor unique enhancements, bit 0 2 this bit is a read only value indicating whether the group code field in the scsi instruction is standard or vendor unique. if cleared, the bit indicates standard group codes; if set, the bit indicates vendor unique group codes. the value in this bit is reloaded at the beginning of all asynchronous target receives. vue1 vendor unique enhancement, bit 1 1 this bit is used to disable the automatic byte count reload during block move instructions in the command phase. if this bit is cleared, the device reloads the block move byte count if the first byte received is one of the standard
4-28 registers group codes. if this bit is set, the device does not reload the block move byte count, regardless of the group code. wsr wide scsi receive 0 when read, this bit returns the value of the wide scsi receive (wsr) flag. setting this bit clears the wsr flag. this clearing function is self-clearing. the wsr flag indicates that the scsi core received data from the scsi bus, detected a possible partial transfer at the end of a chained or nonchained block move command, and temporarily stored the high-order byte in the scsi wide residue (swide) register rather than passing the byte out the dma channel. the hardware uses the wsr status flag to determine what behavior must occur at the start of the next data receive transfer. when the flag is set, the stored data in swide may be ?residue? data, valid data for a subsequent data transfer, or overrun data. the byte is read as normal data by starting a data receive transfer. performing a scsi send operation clears this bit. also, performing any nonwide transfer clears this bit. register: 0x03 scsi control three (scntl3) read/write use ultra scsi enable 7 setting this bit enables ultra scsi synchronous transfers. the default value of this bit is 0. this bit should remain cleared if the LSI53C875A is not operating in ultra scsi mode. when this bit is set, the signal filtering period for sreq/ and sack/ automatically changes to 15 ns for ultra scsi, regardless of the value of the extend req/ack filtering bit in the s c s i te s t tw o ( s t e s t 2 ) register. note: set this bit to achieve ultra scsi transfer rates in legacy systems that use an 80 mhz clock. 76 432 0 use scf[2:0] ews ccf[2:0] 00000000
scsi registers 4-29 scf[2:0] synchronous clock conversion factor [6:4] these bits select a factor by which the frequency of sclk is divided before being presented to the synchronous scsi control logic. write these to the same value as the clock conversion factor bits below unless fast scsi operation is desired. see the scsi transfer (sxfer) register description for examples of how the scf bits are used to calculate synchronous transfer periods. see the table under the description of bits [7:5] of the sxfer register for the valid combinations. ews enablewidescsi 3 when this bit is clear, all information transfer phases are assumed to be eight bits, transmitted on sd[7:0]/ and sdp0/. when this bit is asserted, data transfers are done 16 bits at a time, with the least significant byte on sd[7:0]/ and sdp0/ and the most significant byte on sd[15:8]/, sdp1/. command, status, and message phases are not affected by this bit. ccf[2:0] clock conversion factor [2:0] these bits select a factor by which the frequency of sclk is divided before being presented to the scsi core. the synchronous portion of the scsi core can be run at a different clock rate for fast scsi, using the synchronous clock conversion factor bits. the bit encoding is displayed in the table below. all other combinations are reserved. note: it is important that these bits are set to the proper values to guarantee that the LSI53C875A meets the scsi timings as defined by the ansi specification. scf2 ccf2 scf1 ccf1 scf0 ccf0 factor frequency scsi clock (mhz) 0 0 0 sclk/3 50.01?75.0 0 0 1 sclk/1 16.67?25.0 0 1 0 sclk/1.5 25.01?37.5 0 1 1 sclk/2 37.51?50.0 1 0 0 sclk/3 50.01?75.0 1 0 1 sclk/4 75.01?80.00 1 1 0 sclk/6 120 1 1 1 sclk/8 160
4-30 registers register: 0x04 scsi chip id (scid) read/write r reserved 7 rre enable response to reselection 6 when this bit is set, the LSI53C875A is enabled to respond to bus-initiated reselection at the chip id in the response id zero (respid0) and response id one (respid1) registers. note that the chip does not automatically reconfigure itself to the initiator mode as a result of being reselected. sre enable response to selection 5 when this bit is set, the LSI53C875A is able to respond to bus-initiated selection at the chip id in the respid0 and respid1 registers. note that the chip does not automatically reconfigure itself to target mode as a result of being selected. r reserved 4 enc encoded chip scsi id [3:0] these bits are used to store the LSI53C875A encoded scsi id. this is the id which the chip asserts when arbitrating for the scsi bus. the ids that the LSI53C875A responds to when selected or reselected areconfiguredinthe response id zero (respid0) and response id one (respid1) registers. the priority of the16possibleids,indescendingorderis: 76543 0 r rre sre renc x00 x0000 highest lowest 7654321015141312111098
scsi registers 4-31 register: 0x05 scsi transfer (sxfer) read/write note: when using table indirect i/o commands, bits [7:0] of this register are loaded from the i/o data structure. tp[2:0] scsi synchronous transfer period [7:5] these bits determine the scsi synchronous transfer period used by the LSI53C875A when sending synchronous scsi data in either the initiator or target mode. these bits control the programmable dividers in the chip. the synchronous transfer period the LSI53C875A should usewhentransferringscsidataisdeterminedinthe following example: the LSI53C875A is connected to a hard disk which can transfer data at 10 mbytes/s synchronously. the LSI53C875A?s sclk is running at 40 mhz. the synchronous transfer period ( scsi transfer (sxfer) )is found as follows: sxferp = period/sscp + extcc period = 1 frequency = 1 10 mbytes/s = 100 ns sscp = 1 = sscf = 1 40 mhz = 25 ns 754 0 tp[2:0] mo[4:0] 00000000 tp2 tp1 tp0 xferp 000 4 001 5 010 6 011 7 100 8 101 9 110 10 111 11
4-32 registers (this scsi synchronous core clock is determined in scntl3 bits [6:4], extcc = 1 if scntl1 bit 7 is asserted and the LSI53C875A is sending data. extcc = 0 if the LSI53C875A is receiving data.) sxferp = 100 25 = 4 where: ta b l e 4 . 3 shows examples of synchronous transfer periods and rates for scsi-1. sxferp synchronous transfer period. sscp scsi synchronous core period. sscf scsi synchronous core frequency. extcc extra clock cycle of data setup. table 4.3 examples of synchronous transfer periods and rates for scsi-1 clk (mhz) scsi clk scntl3 bits [6:4] xferp (sxfer bits [7:5]) synch. transfer period (ns) synch. transfer rate (mbytes/s) 66.67 3 4 180 5.55 66.67 3 5 225 4.44 50 2 4 160 6.25 50 2 5 200 5 40 2 4 200 5 37.50 1.5 4 160 6.25 33.33 1.5 4 180 5.55 25 1 4 160 6.25 20 1 4 200 5 16.67 1 4 240 4.17
scsi registers 4-33 ta b l e 4 . 4 shows example transfer periods and rates for fast scsi-2 and ultra scsi. mo[4:0] max scsi synchronous offset [4:0] these bits describe the maximum scsi synchronous offset used by the LSI53C875A when transferring synchronous scsi data in either the initiator or target mode. ta b l e 4 . 5 describes the possible combinations and their relationship to the synchronous data offset used by the LSI53C875A. these bits determine the LSI53C875A?s method of transfer for data-in and data-out phases only; all other information transfers occur asynchronously. table 4.4 example transfer periods and rates for fast scsi-2 and ultra scsi clk (mhz) scsi clk scntl3 bits [6:4] xferp synch. transfer period (ns) synch. transfer rate (mbytes/s) 160 1 1. only with 40 mhz clock. 24 50 20 160 1 4 4 100 10 80 1 4 50 20 50 1 4 80 12.5 50 1 5 100 10.0 40 1 4 100 10.0 37.50 1 4 106.67 9.375 33.33 1 4 120 8.33 25 1 4 160 6.25 20 1 4 200 5 16.67 1 4 240 4.17
4-34 registers table 4.5 maximum synchronous offset mo4 mo3 mo2 mo1 mo0 synchronous offset 00000 0-asynchronous 00001 1 00010 2 00011 3 00100 4 00101 5 00110 6 00111 7 01000 8 01001 9 01010 10 01011 11 01100 12 01101 13 01110 14 01111 15 10000 16 10001 17 10010 18 10011 19 10100 20 10101 21 10110 22 10111 23 11000 24 11001 25 11010 26 11011 27 11100 28 11101 29 11110 30 11111 31
scsi registers 4-35 register: 0x06 scsi destination id (sdid) read/write r reserved [7:4] enc encoded destination scsi id [3:0] writing these bits set the scsi id of the intended initiator or target during scsi reselection or selection phases, respectively. when executing scripts, the scripts processor writes the destination scsi id to this register. the scsi id is defined by the user in a scripts select or reselect instruction. the value written is the binary-encoded id. the priority of the 16 possible ids, in descending order, is: register: 0x07 general purpose (gpreg0) read/write reads to this register will always yield the same values. a write to this register will cause the data written to be output to the appropriate gpio pin if it is set to the output mode in the general purpose pin control zero (gpcntl0) register. r reserved [7:5] gpio general purpose i/o [4:0] these bits are programmed through the general purpose pin control zero (gpcntl0) register as inputs, outputs, or to perform special functions. as an output, these pins can be used to enable or disable external terminators. it 7430 renc x x x x0000 highest lowest 7654321015141312111098 754 0 rgpio x x x0xxxx
4-36 registers is also possible to program these signals as live inputs and sense them through a scripts register to register move instruction. gpio4 may be used to enable or disable v pp , the 12 volt power supply to the external flash memory. this bit powers up with the power to external memory disabled. gpio[3:0] default as inputs and gpio4 defaults as an output pin. when configured as inputs, an internal pull-down is enabled for gpio[4:2]. for gpio[1:0], internal pull-ups are enabled. lsi logic software uses the gpio[1:0] signals to access serial eeprom. gpio1 is used as a clock, with the gpio0 pin serving as data. lsi logic software also reserves the use of gpio[4:2]. if there is a need to use gpio[4:2] please check with lsi logic for additional information. register: 0x08 scsi first byte received (sfbr) read/write sfbr scsi first byte received [7:0] this register contains the first byte received in any asynchronous information transfer phase. for example, when a LSI53C875A is operating in the initiator mode, this register contains the first byte received in the message-in, status phase, and data-in phases. when a block move instruction is executed for a particular phase, the first byte received is stored in this register, even if the present phase is the same as the last phase. the first byte received for a particular input phase is not valid until after a move instruction is executed. this register is also the accumulator for register read- modify-writes with the sfbr as the destination. this allows bit testing after an operation. the sfbr is not writable using the cpu, and therefore not by a memory move. however, it can be loaded using scripts read/write operations. to load the sfbr with 7 0 sfbr 00000000
scsi registers 4-37 abytestoredinsystemmemory,thebytemustfirstbe moved to an intermediate LSI53C875A register (such as a scratch register), and then to the sfbr. this register also contains the state of the lower eight bits of the scsi data bus during the selection phase if the com bit in the dma control (dcntl) register is clear. if the com bit is cleared, do not access this register using scripts operations, as nondeterminate operations may occur. this includes scripts read/write operations and conditional transfer control instructions that initialize the sfbr register. register: 0x09 scsi output control latch (socl) read/write req assert scsi req/ signal 7 ack assert scsi ack/ signal 6 bsy assert scsi bsy/ signal 5 sel assert scsi sel/ signal 4 atn assert scsi atn/ signal 3 msg assert scsi msg/ signal 2 c_d assert scsi c_d/ signal 1 i/o assert scsi i_o/ signal 0 this register is used primarily for diagnostic testing or programmed i/o operation. it is controlled by the scripts processor when executing scsi scripts. socl is used only when transferring data using programmed i/o. some bits are set (1) or cleared (0) when executing scsi scripts. do not write to the register once the LSI53C875A starts executing normal scsi scripts. 76543210 req ack bsy sel atn msg c_d i/o 00000000
4-38 registers register: 0x0a scsi selector id (ssid) read only val scsi valid 7 if val is asserted, then the two scsi ids are detected on the bus during a bus-initiated selection or reselection, and the encoded destination scsi id bits below are valid. if val is deasserted, only one id is present and the contents of the encoded destination id are meaningless. r reserved [6:4] enid encoded destination scsi id [3:0] reading the ssid register immediately after the LSI53C875A is selected or reselected returns the binary-encoded scsi id of the device that performed the operation. these bits are invalid for targets that are selected under the single initiator option of the scsi-1 specification. this condition is detected by examining the val bit above. register: 0x0b scsi bus control lines (sbcl) read only this register returns the scsi control line status. a bit is set when the corresponding scsi control line is asserted. these bits are not latched; they are a true representation of what is on the scsi bus at the time the register is read. the resulting read data is synchronized before being presented to the pci bus to prevent parity errors from being passed to the system. this register is used for diagnostic testing or operation in low level mode. 76 43 0 val renid 0 x x x0000 76543210 req ack bsy sel atn msg c_d i_o xxxxxxxx
scsi registers 4-39 req sreq/ status 7 ack sack/ status 6 bsy sbsy/ status 5 sel ssel/ status 4 atn satn/ s tatus 3 msg smsg/ status 2 c_d sc_d/ status 1 i_o si_o/ status 0 register: 0x0c dma status (dstat) read only reading this register clears any bits that are set at the time the register is read, but does not necessarily clear the register in case additional interrupts are pending (the LSI53C875A stacks interrupts). the dip bit in the interrupt status zero (istat0) register is also cleared. it is possible to mask dma interrupt conditions individually through the dma interrupt enable (dien) register. when performing consecutive 8-bit reads of the dstat, scsi interrupt status zero (sist0) and scsi interrupt status one (sist1) registers (in any order), insert a delay equivalent to 12 clk periods between the reads to ensure that the interrupts clear properly. see chapter 2, ?functional description? for more information on interrupts. dfe dma fifo empty 7 this status bit is set when the dma fifo is empty. it is possible to use it to determine if any data resides in the fifo when an error occurs and an interrupt is generated. this bit is a pure status bit and does not cause an interrupt. 76543210 dfe mdpe bf abrt ssi sir riid 100000 x0
4-40 registers mdpe master data parity error 6 this bit is set when the LSI53C875A as a master detects a data parity error, or a target device signals a parity error during a data phase. this bit is completely disabled by the master parity error enable bit (bit 3 of chip test four (ctest4) ). bf bus fault 5 this bit is set when a pci bus fault condition is detected. a pci bus fault can only occur when the LSI53C875A is bus master, and is defined as a cycle that ends with a bad address or target abort condition. abrt aborted 4 this bit is set when an abort condition occurs. an abort condition occurs when a software abort command is issued by setting bit 7 of the interrupt status zero (istat0) register. ssi single step interrupt 3 if the single step mode bit in the dma control (dcntl) register is set, this bit is set and an interrupt is generated after successful execution of each scripts instruction. sir scripts interrupt instruction received 2 this status bit is set whenever an interrupt instruction is evaluated as true. r reserved 1 iid illegal instruction detected 0 this status bit is set any time an illegal or reserved instruction opcode is detected, whether the LSI53C875A is operating in single step mode or automatically executing scsi scripts. any of the following conditions during instruction execution also set this bit: ? the LSI53C875A is executing a wait disconnect instruction and the scsi req line is asserted without a disconnect occurring. ? a block move instruction is executed with 0x000000 loadedintothe dma byte counter (dbc) register, indicating there are zero bytes to move.
scsi registers 4-41 ? during a transfer control instruction, the compare data (bit 18) and compare phase (bit 17) bits are set in the dma byte counter (dbc) register while the LSI53C875A is in target mode. ? during a transfer control instruction, the carry test bit (bit 21) is set and either the compare data (bit 18) or compare phase (bit 17) bit is set. ? a transfer control instruction is executed with the reserved bit 22 set. ? a transfer control instruction is executed with the wait for valid phase bit (bit 16) set while the chip is in target mode. ? aload/storeinstructionisissuedwiththe memory address mapped to the operating registers of the chip, not including rom or ram. ? a load/store instruction is issued when the register address is not aligned with the memory address. ? a load/store instruction is issued with bit 5 in the dma command (dcmd) register cleared or bits 3 or 2set. ? a load/store instruction when the count value in the dma byte counter (dbc) register is not set at 1 to 4. ? a load/store instruction attempts to cross a dword boundary. ? a memory move instruction is executed with one of the reserved bits in the dma command (dcmd) register set. ? a memory move instruction is executed with the source and destination addresses not aligned. ? a 64-bit table indirect block move instruction is executed with a selector index value greater than 0x16. ? if the select with atn/ bit 24 is set for any i/o instruction other than a select instruction.
4-42 registers register: 0x0d scsi status zero (sstat0) read only ilf sidl least significant byte full 7 this bit is set when the least significant byte in the scsi input data latch (sidl) register contains data. data is transferred from the scsi bus to the scsi input data latch register before being sent to the dma fifo and then to the host bus. the sidl register contains scsi data received asynchronously. synchronous data received does not flow through this register. orf sodr least significant byte full 6 this bit is set when the least significant byte in the scsi output data register (sodr, a hidden buffer register which is not accessible) contains data. the sodr is used by the scsi logic as a second storage register when sending data synchronously. it is not readable or writable by the user. it is possible to use this bit to determine how many bytes reside in the chip when an error occurs. olf sodl least significant byte full 5 this bit is set when the least significant byte in the scsi output data latch (sodl) contains data. the sodl register is the interface between the dma logic and the scsi bus. in synchronous mode, data is transferred from the host bus to the sodl register, and then to the scsi output data register (sodr, a hidden buffer register which is not accessible) before being sent to the scsi bus. in asynchronous mode, data is transferred from the host bus to the sodl register, and then to the scsi bus. the sodr buffer register is not used for asynchronous transfers. it is possible to use this bit to determine how many bytes reside in the chip when an error occurs. 76543210 ilf orf olf aip loa woa rst sdp0 00000000
scsi registers 4-43 aip arbitration in progress 4 arbitration in progress (aip = 1) indicates that the LSI53C875A has detected a bus free condition, asserted sbsy, and asserted its scsi id onto the scsi bus. loa lost arbitration 3 when set, loa indicates that the LSI53C875A has detected a bus free condition, arbitrated for the scsi bus, and lost arbitration due to another scsi device asserting the ssel/ signal. woa won arbitration 2 when set, woa indicates that the LSI53C875A has detected a bus free condition, arbitrated for the scsi bus and won arbitration. the arbitration mode selected in the scsi control zero (scntl0) register must be full arbitration and selection to set this bit. rst scsirst/signal 1 this bit reports the current status of the scsi rst/ signal, and the srst signal (bit 6) in the interrupt status zero (istat0) register. this bit is not latched and may change as it is read. sdp0 scsi sdp0/ parity signal 0 this bit represents the active high current status of the scsi sdp0/ parity signal. this signal is not latched and maychangeasitisread. register: 0x0e scsi status one (sstat1) read only ff[3:0] fifo flags [7:4] these four bits, along with scsi status two (sstat2) bit 4, define the number of bytes or words that currently reside in the LSI53C875A?s scsi synchronous data fifo as shown in ta bl e 4 . 6 . these bits are not latched and they will change as data moves through the fifo. the scsififocanholdupto31bytesfornarrowscsi 7 43210 ff[3:0] sdp0l msg c_d i_o 0000 xxxx
4-44 registers synchronous data transfers, or up to 31 words for wide. values over 31 will not occur. table 4.6 scsi synchronous data fifo word count ff4 (sstat2 bit 4) ff3 ff2 ff1 ff0 bytes or words in the scsi fifo 0 0000 0 0 0001 1 0 0010 2 0 0011 3 0 0100 4 0 0101 5 0 0110 6 0 0111 7 0 1000 8 0 1001 9 0 1010 10 0 1011 11 0 1100 12 0 1101 13 0 1110 14 0 1111 15 1 0000 16 1 0001 17 1 0010 18
scsi registers 4-45 sdp0l latched scsi parity 3 this bit reflects the scsi parity signal (sdp0/), corresponding to the data latched in the scsi input data latch (sidl) . it changes when a new byte is latched into the least significant byte of the sidl register. this bit is active high, in other words, it is set when the parity signal is active. msg scsimsg/signal 2 c_d scsic_d/signal 1 i_o scsii_o/signal 0 these three scsi phase status bits (msg, c_d, and i_o) are latched on the asserting edge of sreq/ when operating in either the initiator or target mode. these bits are set when the corresponding signal is active. they are useful when operating in the low level mode. 1 0011 19 1 0100 20 1 0101 21 1 0110 22 1 0111 23 1 1000 24 1 1001 25 1 1010 26 1 1011 27 1 1100 28 1 1101 29 1 1110 30 1 1111 31 table 4.6 scsi synchronous data fifo word count (cont.) ff4 (sstat2 bit 4) ff3 ff2 ff1 ff0 bytes or words in the scsi fifo
4-46 registers register: 0x0f scsi status two (sstat2) read only ilf1 sidl most significant byte full 7 this bit is set when the most significant byte in the scsi input data latch (sidl) contains data. data is transferred from the scsi bus to the scsi input data latch register before being sent to the dma fifo and then to the host bus. the sidl register contains scsi data received asynchronously. synchronous data received does not flow through this register. orf1 sodr most significant byte full 6 this bit is set when the most significant byte in the scsi output data register (sodr, a hidden buffer register which is not accessible) contains data. the sodr register is used by the scsi logic as a second storage register when sending data synchronously. it is not accessible to the user. this bit is used to determine how many bytes reside in the chip when an error occurs. olf1 sodl most significant byte full 5 this bit is set when the most significant byte in the scsi output data latch (sodl) contains data. the sodl register is the interface between the dma logic and the scsi bus. in synchronous mode, data is transferred from the host bus to the sodl register, and then to the scsi output data register (sodr, a hidden buffer register which is not accessible) before being sent to the scsi bus. in asynchronous mode, data is transferred from the host bus to the sodl register, and then to the scsi bus. the sodr buffer register is not used for asynchronous transfers. it is possible to use this bit to determine how many bytes reside in the chip when an error occurs. ff4 fifo flags, bit 4 4 this is the most significant bit in the scsi fifo flags field, when concatenated with bits [7:4] (ff[3:0]) in scsi status one (sstat1) . for a complete description of this 76543210 ilf1 orf1 olf1 ff4 spl1 r ldsc sdp1 0000x x1x
scsi registers 4-47 field, see the definition for scsi status one (sstat1) bits [7:4]. spl1 latched scsi parity for sd[15:8] 3 this active high bit reflects the scsi odd parity signal corresponding to the data latched into the most significantbyteinthe scsi input data latch (sidl) register. r reserved 2 ldsc last disconnect 1 this bit is used in conjunction with the connected (con) bit in scsi control one (scntl1) .itallowstheuserto detect the case in which a target device disconnects, and then some scsi device selects or reselects the LSI53C875A. if the connected bit is asserted and the ldsc bit is asserted, a disconnect is indicated. this bit is set when the connected bit in scntl1 is off. this bit is cleared when a block move instruction is executed while the connected bit in scntl1 is on. sdp1 scsi sdp1 signal 0 this bit represents the active high current state of the scsi sdp1 parity signal. it is unlatched and may change as it is read. registers: 0x10?0x13 data structure address (dsa) read/write dsa data structure address [31:0] this 32-bit register contains the base address used for all table indirect calculations. the dsa register is usually loaded prior to starting an i/o, but it is possible for a scripts memory move to load the dsa during the i/o. during any memory-to-memory move operation, the contents of this register are preserved. the power-up value of this register is indeterminate. 31 0 dsa 00000000000000000000000000000000
4-48 registers register: 0x14 interrupt status zero (istat0) read/write this register is accessible by the host cpu while a LSI53C875A is executing scripts (without interfering in the operation of the function). it is used to poll for interrupts if hardware interrupts are disabled. read this register after servicing an interrupt to check for stacked interrupts. abrt abort operation 7 setting this bit aborts the current operation under execution by the LSI53C875A. if this bit is set and an interrupt is received, clear this bit before reading the dma status (dstat) register to prevent further aborted interrupts from being generated. the sequence to abort any operation is: 1. set this bit. 2. wait for an interrupt. 3. read the interrupt status zero (istat0) and interrupt status one (istat1) registers. 4. if the scsi interrupt pending bit is set, then read the scsi interrupt status zero (sist0) or scsi interrupt status one (sist1) register to determine the cause ofthescsiinterruptandgobacktostep2. 5. if the scsi interrupt pending bit is clear, and the dma interrupt pending bit is set, then write 0x00 value to this register. 6. read the dma status (dstat) register to verify the aborted interrupt and to see if any other interrupting conditions have occurred. srst software reset 6 setting this bit resets the LSI53C875A. all operating registers are cleared to their respective default values and all scsi signals are deasserted. setting this bit does not assert the scsi rst/ signal. this reset does not 76543210 abrt srst sigp sem con intf sip dip 00000000
scsi registers 4-49 clear the id mode bit or any of the pci configuration registers. this bit is not self-clearing; it must be cleared to clear the reset condition (a hardware reset also clears this bit). sigp signal process 5 sigp is a r/w bit that is writable at any time, and polled and reset using c h i p te s t tw o ( c t e s t 2 ) .thesigpbit is used in various ways to pass a flag to or from a running scripts instruction. the only scripts instruction directly affected by the sigp bit is wait for selection/reselection. setting this bit causes that instruction to jump to the alternate address immediately. the instructions at the alternate jump address should check the status of sigp to determine the cause of the jump. the sigp bit is usable at any time and is not restricted to the wait for selection/reselection condition. sem semaphore 4 the scripts processor may set this bit using a scripts register write instruction. an external processor may also set it while the LSI53C875A is executing a scripts operation. this bit enables the LSI53C875A to notify an external processor of a predefined condition while scripts are running. the external processor may also notify the LSI53C875A of a predefined condition and the scripts processor may take action while scripts are executing. con connected 3 this bit is automatically set any time the LSI53C875A is connected to the scsi bus as an initiator or as a target. it is set after successfully completing selection or when the LSI53C875A responds to a bus-initiated selection or reselection. it is also set after the LSI53C875A wins arbitration when operating in low level mode. when this bit is clear, the LSI53C875A is not connected to the scsi bus. intf interrupt-on-the-fly 2 this bit is asserted by an intfly instruction during scripts execution. scripts programs do not halt whentheinterruptoccurs.thisbitcanbeusedtonotify a service routine, running on the main processor while
4-50 registers the scripts processor is still executing a scripts program. if this bit is set when the interrupt status zero (istat0) or interrupt status one (istat1) registers are read they are not automatically cleared. to clear this bit, write it to a one. the reset operation is self-clearing. note: if the intf bit is set but sip or dip are not set, do not attempt to read the other chip status registers. an interrupt-on-the-fly interrupt must be cleared before servicing any other interrupts indicated by sip or dip. this bit must be written to one in order to clear it after it has been set. sip scsi interrupt pending 1 this status bit is set when an interrupt condition is detected in the scsi portion of the LSI53C875A. the following conditions cause a scsi interrupt to occur: ? a phase mismatch (initiator mode) or satn/ becomes active (target mode) ? an arbitration sequence completes ? a selection or reselection time-out occurs ? the LSI53C875A is selected ? the LSI53C875A is reselected ? a scsi gross error occurs ? an unexpected disconnect occurs ? a scsi reset occurs ? a parity error is detected ? the handshake-to-handshake timer is expired ? the general purpose timer is expired to determine exactly which condition(s) caused the interrupt, read the scsi interrupt status zero (sist0) and scsi interrupt status one (sist1) registers. dip dma interrupt pending 0 this status bit is set when an interrupt condition is detected in the dma portion of the LSI53C875A. the following conditions cause a dma interrupt: ? a pci parity error is detected
scsi registers 4-51 ? a bus fault is detected ? an abort condition is detected ? a scripts instruction is executed in single step mode ? a scripts interrupt instruction is executed ? an illegal instruction is detected to determine exactly which condition(s) caused the interrupt, read the dma status (dstat) register. register: 0x15 interrupt status one (istat1) read/write r reserved [7:3] flsh flushing 2 reading this bit monitors if the chip is currently flushing data. if set, the chip is flushing data from the dma fifo. if cleared, no flushing is occurring. this bit is read only and writes will have no effect on the value of this bit. srun scripts running 1 this bit indicates whether or not the scripts engine is currently fetching and executing scripts instructions. if this bit is set, the scripts engine is active. if it is cleared, the scripts engine is not active. this bit is read only and writes will have no effect on the value of this bit. si sync_irqd 0 setting this bit disables the irq/ pin. clearing this bit enables normal operation of the irq/ pin. the function of this bit is nearly identical to bit 1 of the dma control (dcntl) ( 0x3b ) register except that if the irq/ is already asserted and this bit is set, irq/ will remain asserted until the interrupt is serviced. at this point the irq/ line will be blocked for future interrupts until this bit is cleared. in 7 3210 rflshsrunsi x x x x x000
4-52 registers addition, this bit may be read and written while scripts are executing. register: 0x16 mailbox zero (mbox0) read/write mbox0 mailbox zero [7:0] these are general purpose bits that may be read or written while scripts are running. they also may be read or written by the scripts processor. note: the host and the scripts processor code could potentially attempt to access the same mailbox byte at the same time. using one mailbox register as a read only and the other as a write only will prevent this type of conflict. register: 0x17 mailbox one (mbox1) read/write mbox1 mailbox one [7:0] these are general purpose bits that may be read or written while scripts are running. they also may be read or written by the scripts processor. note: the host and the scripts processor code could potentially attempt to access the same mailbox byte at the same time. using one mailbox register as a read only and the other as a write only will prevent this type of conflict. 7 0 mbox0 00000000 7 0 mbox1 00000000
scsi registers 4-53 register: 0x18 chip test zero (ctest0) read/write fmt byte empty in dma fifo [7:0] these bits identify the bottom bytes in the dma fifo that are empty. each bit corresponds to a byte lane in the dma fifo. for example, if byte lane three is empty, then fmt3 will be set. since the fmt flags indicate the status of bytes at the bottom of the fifo, if all fmt bits are set, the dma fifo is empty. register: 0x19 chip test one (ctest1) read only ffl byte full in dma fifo [7:0] these status bits identify the top bytes in the dma fifo that are full. each bit corresponds to a byte lane in the dma fifo. for example, if byte lane three is full then ffl3 is set. since the ffl flags indicate the status of bytes at the top of the fifo, if all ffl bits are set, the dma fifo is full. 7 0 fmt 11111111 7 0 ffl 00000000
4-54 registers register: 0x1a chip test two (ctest2) read only (bit 3 write) ddir data transfer direction 7 this status bit indicates which direction data is being transferred. when this bit is set, the data is transferred from the scsi bus to the host bus. when this bit is clear, the data is transferred from the host bus to the scsi bus. sigp signal process 6 this bit is a copy of the sigp bit in the interrupt status zero (istat0) register (bit = 5). the sigp bit is used to signal a running scripts instruction. when this register is read, the sigp bit in the interrupt status zero (istat0) register is cleared. cio configured as i/o 5 this bit is defined as the configuration i/o enable status bit. this read only bit indicates if the chip is currently enabled as i/o space. cm configured as memory 4 this bit is defined as the configuration memory enable status bit. this read only bit indicates if the chip is currently enabled as memory space. note: bits 4 and 5 may be set if the chip is mapped in both i/o and memory space. also, bits 4 and 5 may be set if the chip is dual-mapped. pcicie pci configuration into enable 3 this bit controls the shadowing of the pci base address register one (memory) ,pci base address register two (scripts ram) ,pcideviceid,andpcirevision id into the scratch register a (scratcha) , scratch register b (scratchb) , and scripts fetch selector (sfs) registers. when it is set, the scratcha register contains bits [31:0] of the memory base address value from the pci 76543210 ddir sigp cio cm pcicie teop dreq dack 00xx0001
scsi registers 4-55 base address register one (memory) .thisisthe memory mapped operating register base address. bits [9:0] will be 0. the scratchb register contains bits [31:13] of the ram base address value from the pci base address register two (scripts ram) .thisisthe base address for the internal 4 kbytes ram. bits [11:0] will be 0. bits [23:16] of scripts fetch selector (sfs) contain the pci revision id (rev id) register value and bits [15:0] contain the pci device id register value. when this bit is set, writes to this register have no effect. when this bit is cleared, the scratch register a (scratcha) , scratch register b (scratchb) ,and scripts fetch selector (sfs) registers return to normal operation. note: bit 3 is the only writable bit in this register. all other bits are read only. when modifying this register, all other bits must be written to zero. do not execute a read-modify-write to this register. teop scsi true end of process 2 this bit indicates the status of the LSI53C875A?s teop signal. the teop signal acknowledges the completion of a transfer through the scsi portion of the LSI53C875A. when this bit is set, teop is active. when this bit is clear, teop is inactive. dreq data request status 1 this bit indicates the status of the LSI53C875A?s internal data request signal (dreq). when this bit is set, dreq is active. when this bit is clear, dreq is inactive. dack data acknowledge status 0 this bit indicates the status of the LSI53C875A?s internal data acknowledge signal (dack/). when this bit is set, dack/isinactive.whenthisbitisclear,dack/isactive.
4-56 registers register: 0x1b chip test three (ctest3) read/write v chiprevisionlevel [7:4] these bits identify the chip revision level for software purposes. it should have the same value as the lower nibble of the pci revision id (rev id) register, at address 0x08 in the configuration space. flf flush dma fifo 3 when this bit is set, data residing in the dma fifo is transferred to memory, starting at the address in the dma next address 64 (dnad64) register. the internal dmawr signal, controlled by the chip test five (ctest5) register, determines the direction of the transfer. this bit is not self-clearing; clear it once the data is successfully transferred by the LSI53C875A. note: polling of fifo flags is allowed during flush operations. clf clear dma fifo 2 when this bit is set, all data pointers for the dma fifo are cleared. any data in the fifo is lost. after the LSI53C875A successfully clears the appropriate fifo pointers and registers, this bit automatically clears. note: this bit does not clear the data visible at the bottom of the fifo. fm fetch pin mode 1 when set, this bit causes the fetch/ pin to deassert during indirect and table indirect read operations. fetch/ is only active during the opcode portion of an instruction fetch. this allows the storage of scripts in a prom while data tables are stored in ram. if this bit is not set, fetch/ is asserted for all bus cycles during instruction fetches. 7 43210 v flf clf fm wrie xxxx0000
scsi registers 4-57 wrie write and invalidate enable 0 this bit, when set, causes the issuing of write and invalidate commands on the pci bus whenever legal. the write and invalidate enable bit in the pci configuration command register must also be set in order for the chip to generate write and invalidate commands. registers: 0x1c?0x1f temporary (temp) read/write temp temporary [31:0] this 32-bit register stores the return instruction address pointer from the call instruction. the address pointer stored in this register is loaded into the dma scripts pointer (dsp) register when a return instruction is executed. this address points to the next instruction to execute. do not write to this register while the LSI53C875A is executing scripts. during any memory-to-memory move operation, the contents of this register are preserved. the power-up value of this register is indeterminate. register: 0x20 dma fifo (dfifo) read/write bo byte offset counter [7:0] these bits, along with bits [1:0] in the chip test five (ctest5) register, indicate the amount of data transferred between the scsi core and the dma core. it is used to determine the number of bytes in the dma fifo when an interrupt occurs. these bits are unstable 31 0 temp 00000000000000000000000000000000 7 0 bo 00000000
4-58 registers while data is being transferred between the two cores. once the chip has stopped transferring data, these bits are stable. the dma fifo (dfifo) register counts the number of bytes transferred between the dma core and the scsi core. the dma byte counter (dbc) register counts the number of bytes transferred across the host bus. the difference between these two counters represents the number of bytes remaining in the dma fifo. the following steps determine how many bytes are left in the dma fifo when an error occurs, regardless of the transfer direction: if the dfs bit (bit 5, chip test five (ctest5) )isset: 1. subtract the ten least significant bits of the dma byte counter (dbc) register from the 10-bit value of the dfboc. the dfboc consists of the chip test five (ctest5) register, bits 1 and 0 and the dma fifo (dfifo) register, bits [7:0]. 2. and the result with 0x3ff for a byte count between zero and 944. if the dfs bit (bit 5, chip test five (ctest5) ) is cleared: 1. subtract the seven least significant bits of the dma byte counter (dbc) register from the seven bit value ofthedfbocwhichismadeupofthe dma fifo (dfifo) register, bits [6:0]. 2. and the result with 0x7f for a byte count between zero and 112. note: if trying to calculate the total number of bytes in both the dma fifo and scsi logic, see section2.2.12.1?data paths? in chapter 2, ?functional description.?
scsi registers 4-59 register: 0x21 chip test four (ctest4) read/write bdis burst disable 7 when set, this bit causes the LSI53C875A to perform back-to-back cycles for all transfers. when this bit is cleared, back-to-back transfers for opcode fetches and burst transfers for data moves are performed. fbl3 fifo byte control 6 this bit is used with fbl[2:0]. see bits [2:0] description in this register. zsd scsi data high impedance 5 setting this bit causes the LSI53C875A to place the scsi data bus sd[15:0] and the parity lines sdp[1:0] in a high impedance state. in order to transfer data on the scsi bus, clear this bit. srtm shadow register test mode 4 setting this bit allows access to the shadow registers used by memory-to-memory move operations. when this bit is set, register accesses to the temporary (temp) and data structure address (dsa) registers are directed to the shadow copies stemp (shadow temp) and sdsa (shadow dsa). the registers are shadowed to prevent them from being overwritten during a memory-to-memory move operation. the dsa and temp registers contain the base address used for table indirect calculations, and the address pointer for a call or return instruction, respectively. this bit is intended for manufacturing diagnostics only and should not be set during normal operations. mpee master parity error enable 3 setting this bit enables parity checking during master data phases. a parity error during a bus master read is detected by the LSI53C875A. a parity error during a bus master write is detected by the target, and the 765432 0 bdis fbl3 zsd srtm mpee fbl[2:0] 00000000
4-60 registers LSI53C875A is informed of the error by the perr/ pin being asserted by the target. when this bit is cleared, the LSI53C875A does not interrupt if a master parity error occurs. this bit is cleared at power-up. fbl[2:0] fifo byte control [2:0] these bits steer the contents of the chip test six (ctest6) register to the appropriate byte lane of the 64-bit dma fifo. if the fbl3 bit is set, then fbl2 through fbl0 determine which of eight byte lanes can be read or written. when cleared, the byte lane read or written is determined by the current contents of the dma next address (dnad) and dma byte counter (dbc) registers. each of the eight bytes that make up the 64-bit dma fifo is accessed by writing these bits to the proper value. for normal operation, fbl3 must equal zero. register: 0x22 chip test five (ctest5) read/write adck clock address incrementor 7 setting this bit increments the address pointer contained in the dma next address (dnad) register. the dnad register is incremented based on the dnad contents and fbl3 fbl2 fbl1 fbl0 dma fifo byte lane 0 x x x disabled 1000 0 1001 1 1010 2 1011 3 1100 4 1101 5 1110 6 1111 7 76543210 adck bbck dfs masr ddir bl2 bo[9:8] 00000000
scsi registers 4-61 the current dbc value. this bit automatically clears itself after incrementing the dnad register. bbck clock byte counter 6 setting this bit decrements the byte count contained in the 24-bit dbc register. it is decremented based on the dma byte counter (dbc) contents and the current dma next address (dnad) value. this bit automatically clears itself after decrementing the dbc register. dfs dma fifo size 5 this bit controls the size of the dma fifo. when clear, the dma fifo appears as only 112 bytes deep. when set, the dma fifo size increases to 944 bytes. using an 112-byte fifo allows software written for other lsi53c8xx family chips to properly calculate the number of bytes residing in the chip after a target disconnect. the default value of this bit is zero. masr master control for set or reset pulses 4 this bit controls the operation of bit 3. when this bit is set, bit 3 asserts the corresponding signals. when this bit is cleared, bit 3 deasserts the corresponding signals. do not change this bit and bit 3 in the same write cycle. ddir dma direction 3 setting this bit either asserts or deasserts the internal dma write (dmawr) direction signal depending on the current status of the masr bit in this register. asserting the internal dma write signal indicates that data is transferred from the scsi bus to the host bus. deasserting the internal dma write signal transfers data from the host bus to the scsi bus. bl2 burst length bit 2 2 this bit works with bits 6 and 7 (bl[1:0]) in the dma mode (dmode) , 0x38 register to determine the burst length. for complete definitions of this field, refer to the descriptions of dmode bits 6 and 7. this bit is disabled if a 112-byte fifo is selected by clearing the dma fifo size bit.
4-62 registers bo[9:8] dma fifo byte offset counter, bits [9:8] [1:0] these are the upper two bits of the dfboc. the dfboc consists of these bits, and the dma fifo (dfifo) register, bits [7:0]. register: 0x23 chip test six (ctest6) read/write df dma fifo [7:0] writing to this register writes data to the appropriate byte lane of the dma fifo as determined by the fbl bits in the chip test four (ctest4) register. reading this register unloads data from the appropriate byte lane of the dma fifo as determined by the fbl bits in the ctest4 register. data written to the fifo is loaded into the top of the fifo. data read out of the fifo is taken from the bottom. to prevent dma data from being corrupted, this register should not be accessed before starting or restarting scripts operation. write this register only when testing the dma fifo using the ctest4 register. writing to this register while the test mode is not enabled produces unexpected results. registers: 0x24?0x26 dma byte counter (dbc) read/write dbc dma byte counter [23:0] this 24-bit register determines the number of bytes transferred in a block move instruction. while sending data to the scsi bus, the counter is decremented as data is moved into the dma fifo from memory. while receiving data from the scsi bus, the counter is decremented as data is written to memory from the 7 0 df 00000000 23 0 dbc xxxxxxxxxxxxxxxxxxxxxxxx
scsi registers 4-63 LSI53C875A. the dbc counter is decremented each time data is transferred on the pci bus. it is decremented by an amount equal to the number of bytes that are transferred. the maximum number of bytes that can be transferred in any one block move command is 16,777,215 bytes. the maximum value that can be loaded into the dma byte counter (dbc) register is 0xffffff. if the instruction is a block move and a value of 0x000000 is loaded into the dbc register, an illegal instruction interrupt occurs if the LSI53C875A is not in target mode, command phase. the dbc register is also used to hold the least significant 24 bits of the first dword of a scripts fetch, and to hold the offset value during table indirect i/o scripts. for a complete description see chapter 5, ?scsi scripts instruction set? . the power-up value of this register is indeterminate. see section 5.3.1, ?first dword,? for register detail. register: 0x27 dma command (dcmd) read/write dcmd dma command [7:0] this 8-bit register determines the instruction for the LSI53C875A to execute. this register has a different format for each instruction. see section 5.3.1, ?first dword,? for register detail. 7 0 dcmd 01xxxxxx
4-64 registers registers: 0x28?0x2b dma next address (dnad) read/write dnad dma next address [31:0] this 32-bit register contains the general purpose address pointer. at the start of some scripts operations, its value is copied from the dma scripts pointer save (dsps) register. its value may not be valid except in certain abort conditions. the default value of this register is zero. registers: 0x2c?0x2f dma scripts pointer (dsp) read/write dsp dma scripts pointer [31:0] to execute scsi scripts, the address of the first scripts instruction must be written to this register. in normal scripts operation, once the starting address of the script is written to this register, scripts are automatically fetched and executed until an interrupt condition occurs. in single step mode, there is a single step interrupt after each instruction is executed. the dma scripts pointer (dsp) register does not need to be written with the next address, but the start dma bit (bit 2, dma control (dcntl) register) must be set each time the step interrupt occurs to fetch and execute the next scripts command. when writing this register eight bits at a time, writing the upper eight bits begins execution of scsi = scripts. the default value of this register is zero. see section 5.4.2, ?second dword,? forregisterdetail. 31 0 dnad 00000000000000000000000000000000 31 0 dsp 00000000000000000000000000000000
scsi registers 4-65 registers: 0x30?0x33 dma scripts pointer save (dsps) read/write dsps dma scripts pointer save [31:0] this register contains the second dword of a scripts instruction. it is overwritten each time a scripts instruction is fetched. when a scripts interrupt instruction is executed, this register holds the interrupt vector. the power-up value of this register is indeterminate. registers: 0x34?0x37 scratch register a (scratcha) read/write scratcha scratch register a [31:0] this is a general purpose, user-definable scratch pad register. apart from cpu access, only register read/write and memory moves into the scratch register alter its contents. the power-up value of this register is indeterminate. a special mode of this register is enabled by setting the pci configuration into enable bit in the c h i p te s t tw o (ctest2) register. if this bit is set, the scratch a register returns bits [31:10] of the memory mapped operating register pci base address ( base address reg- ister one (memory) ) in bits [31:10] of the scratch reg- ister a (scratcha) when read. bits [9:0] of scratch a will always return zero in this mode. writes to the scratch a register are unaffected. clearing the pci configuration into enable bit causes the scratch a register to return to normal operation. 31 0 dsps xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 31 0 scratcha xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
4-66 registers register: 0x38 dma mode (dmode) read/write bl[1:0] burst length [7:6] these bits control the maximum number of dwords transferred per bus ownership, regardless of whether the transfers are back-to-back, burst, or a combination of both. the LSI53C875A asserts the bus request (req/) output when the dma fifo can accommodate a transfer of at least one burst threshold of data. bus request (req/) is also asserted during start-of-transfer and end-of-transfer cleanup and alignment, even if less than a full burst of transfers is performed. the LSI53C875A inserts a ?fairness delay? of four clks between burst transfers (as set in bl[2:0]) during normal operation. the fairness delay is not inserted during pci retry cycles. this gives the cpu and other bus master devices the opportunity to access the pci bus between bursts. the LSI53C875A will only support burst thresholds of up to 16 dwords in the small fifo mode. setting the burst threshold to higher than 16 dwords in the small fifo mode will yield unexpected results in burst lengths. the big fifo mode is activated by setting bit 5 of the chip test five (ctest5) register. in the big fifo mode, the LSI53C875A will support burst thresholds of up to 128 dwords. 76543210 bl[1:0] siom diom erl ermp bof man 00000000
scsi registers 4-67 siom source i/o memory enable 5 this bit is defined as an i/o memory enable bit for the source address of a memory move or block move command. if this bit is set, then the source address is in i/o space; and if cleared, then the source address is in memory space. this function is useful for register-to-memory operations using the memory move instruction when the LSI53C875A is i/o mapped. bits 4 and 5 of the chip test tw o ( c t e s t 2 ) register are used to determine the configuration status of the LSI53C875A. diom destination i/o memory enable 4 this bit is defined as an i/o memory enable bit for the destination address of a memory move or block move command. if this bit is set, then the destination address is in i/o space; and if cleared, then the destination address is in memory space. this function is useful for memory-to-register operations using the memory move instruction when the LSI53C875A is i/o mapped. bits 4 and 5 of the chip test tw o ( c t e s t 2 ) register are used to determine the configuration status of the LSI53C875A. erl enable read line 3 this bit enables a pci read line command. if this bit is set and the chip is about to execute a read cycle other than an opcode fetch, then the command is 0b1110. bl2 (ctest5 bit 2) bl1 bl0 burst length transfers dwords 0002 4 0014 8 0108 16 0111632 1 1003264 1 10164128 1 11064128 1 1 1 1 reserved reserved 1. the 944-byte fifo must be enabled for these burst sizes.
4-68 registers ermp enable read multiple 2 if this bit is set and cache mode is enabled, a read multiple command is used on all read cycles when it is legal. bof burst opcode fetch enable 1 setting this bit causes the LSI53C875A to fetch instructions in burst mode. specifically, the chip bursts in thefirsttwodwordsofallinstructionsusingasinglebus ownership. if the instruction is a memory-to-memory move type, the third dword is accessed in a subsequent bus ownership. if the instruction is an indirect type, the additional dword is accessed in a subsequent bus ownership. if the instruction is a table indirect block move type, the chip accesses the remaining two dwords in a subsequent bus ownership, thereby fetching the four dwords required in two bursts of two dwords each. if prefetch is enabled, this bit has no effect. this bit also has no effect on fetches out of scripts ram. man manual start mode 0 setting this bit prevents the LSI53C875A from automatically fetching and executing scsi scripts when the dma scripts pointer (dsp) register is written. when this bit is set, the start dma bit in the dma control (dcntl) register must be set to begin scripts execution. clearing this bit causes the LSI53C875A to automatically begin fetching and executing scsi scripts when the dsp register is written. this bit normally is not used for scsi scripts operations.
scsi registers 4-69 register: 0x39 dma interrupt enable (dien) read/write r reserved 7 mdpe master data parity error 6 bf bus fault 5 abrt aborted 4 ssi single step interrupt 3 sir scripts interrupt instruction received 2 r reserved 1 iid illegal instruction detected 0 this register contains the interrupt mask bits corresponding to the interrupting conditions described in the dma status (dstat) register. an interrupt is masked by clearing the appropriate mask bit. masking an interrupt prevents irq/ from being asserted for the corresponding interrupt, but the status bit is still set in the dstat register. masking an interrupt does not prevent setting the interrupt status zero (istat0) dip. all dma interrupts are considered fatal, therefore scripts stops running when this condition occurs, whether or not the interrupt is masked. setting a mask bit enables the assertion of irq/ for the corresponding interrupt. (a masked nonfatal interrupt does not prevent unmasked or fatal interrupts from getting through; interrupt stacking begins when either the interrupt status zero (istat0) sip or dip bit is set.) the irq/ output is latched. once asserted, it will remain asserted until the interrupt is cleared by reading the appropriate status register. masking an interrupt after the irq/ output is asserted does not cause deassertion of irq/. 76543210 r mdpe bf abrt ssi sir riid x00000 x0
4-70 registers for more information on interrupts, see chapter 2, ?functional description? . register: 0x3a scratch byte register (sbr) read/write sbr scratch byte register [7:0] this is a general purpose register. apart from cpu access, only register read/write and memory moves into this register alter its contents. the default value of this register is zero. this register is called the dma watchdog timer on previous lsi53c8xx family products. register: 0x3b dma control (dcntl) read/write clse cachelinesizeenable 7 setting this bit enables the LSI53C875A to sense and react to cache line boundaries set up by the dma mode (dmode) or pci cache line size register, whichever contains the smaller value. clearing this bit disables the cache line size logic and the LSI53C875A monitors the cachelinesizeusingthedmoderegister. pff prefetch flush 6 setting this bit causes the prefetch unit to flush its contents. the bit clears after the flush is complete. pfen prefetch enable 5 setting this bit enables an 8-dword scripts instruction prefetch unit. the prefetch unit, when enabled, will fetch 8 dwords of instructions and instruction operands in bursts of 4 or 8 dwords. prefetching instructions allows 7 0 sbr 00000000 76543210 clse pff pfen ssm irqm std irqd com 00000000
scsi registers 4-71 the LSI53C875A to make more efficient use of the system pci bus, thus improving overall system performance. the unit will flush whenever the pff bit is set, as well as on all transfer control instructions when the transfer conditions are met, on every write to the dma scripts pointer (dsp) , on every regular mmov instruction, and when any interrupt is generated. the unit automatically determines the maximum burst size that it is capable of performing based on the burst length as determined by the values in the dma mode (dmode) register. if the burst threshold is set to 8 dwords the prefetch unit will fetch instructions in two bursts of 4 dwords. if the burst threshold is set to 16 dwords or greater the prefetch unit will fetch instructions in one burst of 8 dwords. burst thresholds of less than 8 dwords will cause the prefetch unit to be disabled. pci cache commands (read line and read multiple) will be issued appropriately if pci caching is enabled. prefetching from scripts ram is not supported and is unnecessary due to the speed of the fetches. when fetching from scripts ram the setting of this bit will have no effect on the fetch mechanism from scripts ram. ssm single step mode 4 setting this bit causes the LSI53C875A to stop after executing each scripts instruction, and generate a single step interrupt. when this bit is cleared the LSI53C875A does not stop after each instruction. it continues fetching and executing instructions until an interrupt condition occurs. for normal scsi scripts operation, keep this bit clear. to restart the LSI53C875A after it generates a scripts step interrupt, read the interrupt status zero (istat0) , interrupt status one (istat1) and dma status (dstat) registers to recognize and clear the interrupt. then set the start dma bit in this register. irqm irq mode 3 when set, this bit enables a totem pole driver for the irq/ pin. when cleared, this bit enables an open drain driver for the irq/ pin with an internal weak pull-up. the bit should remain cleared to retain full pci compliance.
4-72 registers std start dma operation 2 the LSI53C875A fetches a scsi scripts instruction from the address contained in the dma scripts pointer (dsp) register when this bit is set. this bit is required if the LSI53C875A is in one of the following modes: ? manualstartmode?bit0inthe dma mode (dmode) register is set ? singlestepmode?bit4inthe dma control (dcntl) register is set when the LSI53C875A is executing scripts in manual start mode, the start dma bit must be set to start instruction fetches, but need not be set again until an interrupt occurs. when the LSI53C875A is in single step mode, set the start dma bit to restart execution of scripts after a single step interrupt. irqd irq disable 1 setting this bit disables the irq pin. clearing the bit enables normal operation. as with any other register other than interrupt status zero (istat0) and interrupt status one (istat1) , this register cannot be accessed except by a scripts instruction during scripts execution. for more information on the use of this bit in interrupt handling, see chapter 2, ?functional description.? com lsi53c700 compatibility 0 when the com bit is cleared, the LSI53C875A behaves in a manner compatible with the lsi53c700; selection/reselection ids are stored in both the scsi selector id (ssid) and scsi first byte received (sfbr) registers. this bit is not affected by a software reset. if the com bit is cleared, do not access this register using scripts operation as nondeterminate operations may occur. (this includes scripts read/write operations and conditional transfer control instructions that initialize the sfbr register.) when the com bit is set, the id is stored only in the ssid register, protecting the sfbr from being overwritten if a selection/reselection occurs during a dma register-to-register operation.
scsi registers 4-73 registers: 0x3c?0x3f adder sum output (adder) read only adder adder sum output [31:0] this register contains the output of the internal adder, and is used primarily for test purposes. the power-up value for this register is indeterminate. it is used to determine if the correct memory address was calculated for a relative jump scripts instruction. register: 0x40 scsi interrupt enable zero (sien0) read/write this register contains the interrupt mask bits corresponding to the interrupting conditions described in the scsi interrupt status zero (sist0) register. an interrupt is masked by clearing the appropriate mask bit. for more information on interrupts, see chapter 2, ?functional description.? m/a scsi phase mismatch - initiator mode; 7 scsi atn condition - target mode in the initiator mode, this bit is set when the scsi phase asserted by the target and sampled during sreq/ does not match the expected phase in the scsi output control latch (socl) register. this expected phase is automatically written by scsi scripts. in target mode, this bit is set when the initiator asserts satn/. see the disable halt on parity error or satn/ condition bit in the scsi control one (scntl1) register for more information on when this status is actually raised. 31 0 adder 00000000000000000000000000000000 76543210 m/a cmp sel rsl sge udc rst par 00000000
4-74 registers cmp function complete 6 indicates full arbitration and selection sequence is completed. sel selected 5 indicates the LSI53C875A is selected by a scsi initiator device. set the enable response to selection bit in the scsi chip id (scid) register for this to occur. rsl reselected 4 indicates the LSI53C875A is reselected by a scsi target device. set the enable response to reselection bit in the scsi chip id (scid) register for this to occur. sge scsi gross error 3 the following conditions are considered scsi gross errors: ? data underflow ? reading the scsi fifo when no data is present. ? data overflow ? writing to the scsi fifo while it is full. ? offset underflow ? receiving a sack/ pulse in target mode before the corresponding sreq/ is sent. ? offset overflow ? receiving an sreq/ pulse in the initiator mode, and exceeding the maximum offset (defined by the mo[3:0] bits in the scsi transfer (sxfer) register). ? a phase change in the initiator mode, with an outstanding sreq/sack/ offset. ? residual data in scsi fifo ? starting a transfer other than synchronous data receive with data left in the scsi synchronous receive fifo. udc unexpected disconnect 2 this condition only occurs in the initiator mode. it happens when the target to which the LSI53C875A is connected disconnects from the scsi bus unexpectedly. see the scsi disconnect unexpected bit in the scsi control two (scntl2) register for more information on expected versus unexpected disconnects. any disconnect in low level mode causes this condition.
scsi registers 4-75 rst scsi reset condition 1 indicates assertion of the srst/ signal by the LSI53C875A or any other scsi device. this condition is edge-triggered, so multiple interrupts cannot occur because of a single srst/ pulse. pa r sc si pa rit y e rro r 0 indicates detection by the LSI53C875A of a parity error while receiving or sending scsi data. see the disable halt on parity error or satn/ condition bits in the scsi control one (scntl1) register for more information on when this condition is actually raised. register: 0x41 scsi interrupt enable one (sien1) read/write this register contains the interrupt mask bits corresponding to the interrupting conditions described in the scsi interrupt status one (sist1) register. an interrupt is masked by clearing the appropriate mask bit. for more information on interrupts, refer to chapter 2, ?functional description.? r reserved [7:3] sto selection or reselection time-out 2 the scsi device which the LSI53C875A is attempting to select or reselect does not respond within the programmed time-out period. see the description of the scsi timer zero (stime0) register bits [3:0] for more informationonthetime-outtimer. gen general purpose timer expired 1 the general purpose timer is expired. the time measured is the time between enabling and disabling of the timer. see the description of the scsi timer one (stime1) register, bits [3:0], for more information on the general purpose timer. 7 3210 rstogenhth x x x x x000
4-76 registers hth handshake-to-handshake timer expired 0 the handshake-to-handshake timer is expired. the time measured is the scsi request-to-request (target) or acknowledge-to-acknowledge (initiator) period. see the description of the scsi timer zero (stime0) register, bits [7:4], for more information on the handshake- to-handshake timer. register: 0x42 scsi interrupt status zero (sist0) read only reading the sist0 register returns the status of the various interrupt conditions, whether they are enabled in the scsi interrupt enable zero (sien0) register or not. each bit set indicates occurrence of the corresponding condition. reading the sist0 clears the interrupt status. reading this register clears any bits that are set at the time the register is read, but does not necessarily clear the register because additional interrupts may be pending (the LSI53C875A stacks interrupts). scsi interrupt conditions are individually masked through the scsi interrupt enable zero (sien0) register. when performing consecutive 8-bit reads of the dma status (dstat) , scsi interrupt status zero (sist0) , and scsi interrupt status one (sist1) registers (in any order), insert a delay equivalent to 12 clk periods between the reads to ensure the interrupts clear properly. also, if reading the registers when both the interrupt status zero (istat0) sip and dip bits may not be set, read the sist0 and sist1 registers before the dstat register to avoid missing a scsi interrupt. for more information on interrupts, refer to chapter 2, ?functional description.? m/a initiator mode: phase mismatch; target mode: satn/ active 7 in the initiator mode, this bit is set if the scsi phase asserted by the target does not match the instruction. the phase is sampled when sreq/ is asserted by the 76543210 m/a cmp sel rsl sge udc rst par 00000000
scsi registers 4-77 target. in target mode, this bit is set when the satn/ signal is asserted by the initiator. cmp function complete 6 this bit is set when an arbitration only or full arbitration sequence is completed. sel selected 5 this bit is set when the LSI53C875A is selected by another scsi device. the enable response to selection bit must be set in the scsi chip id (scid) register (and the response id zero (respid0) and response id one (respid1) register must hold the chip?s id) for the LSI53C875A to respond to selection attempts. rsl reselected 4 this bit is set when the LSI53C875A is reselected by another scsi device. the enable response to reselection bit must be set in the scid register (and the response id zero (respid0) and response id one (respid1) registers must hold the chip?s id) for the LSI53C875A to respond to reselection attempts. sge scsi gross error 3 this bit is set when the LSI53C875A encounters a scsi gross error condition. the following conditions can result in a scsi gross error condition: ? data underflow ? reading the scsi fifo when no data is present. ? data overflow ? writing too many bytes to the scsi fifo, or the synchronous offset causes overwriting the scsi fifo. ? offset underflow ? the LSI53C875A is operating in target mode and a sack/ pulse is received when the outstanding offset is zero. ? offset overflow ? the other scsi device sends a sreq/ or sack/ pulse with data which exceeds the maximum synchronous offset defined by the scsi transfer (sxfer) register. ? a phase change occurs with an outstanding synchronous offset when the LSI53C875A is operating as an initiator.
4-78 registers ? residual data in the synchronous data fifo ? a transfer other than synchronous data receive is started with data left in the synchronous data fifo. udc unexpected disconnect 2 this bit is set when the LSI53C875A is operating in the initiator mode and the target device unexpectedly disconnects from the scsi bus. this bit is only valid when the LSI53C875A operates in the initiator mode. when the LSI53C875A operates in low level mode, any disconnect causes an interrupt, even a valid scsi disconnect. this bit is also set if a selection time-out occurs (it may occur before, at the same time, or stacked after the sto interrupt, since this is not considered an expected disconnect). rst scsirst/received 1 this bit is set when the LSI53C875A detects an active srst/ signal, whether the reset is generated external to thechiporcausedbytheassertrstbitinthe scsi control one (scntl1) register. this scsi reset detection logic is edge-sensitive, so that multiple interrupts are not generated for a single assertion of the srst/ signal. pa r par ity er ror 0 this bit is set when the LSI53C875A detects a parity error while receiving scsi data. the enable parity checking bit (bit 3 in the scsi control zero (scntl0) register) must be set for this bit to become active. the LSI53C875A always generates parity when sending scsi data. register: 0x43 scsi interrupt status one (sist1) read only reading the sist1 register returns the status of the various interrupt conditions, whether they are enabled in the scsi interrupt enable one 7 3210 rstogenhth x x x x x000
scsi registers 4-79 (sien1) register or not. each bit that is set indicates an occurrence of the corresponding condition. reading the sist1 clears the interrupt condition. r reserved [7:3] sto selection or reselection time-out 2 the scsi device which the LSI53C875A is attempting to select or reselect does not respond within the programmed time-out period. see the description of the scsi timer zero (stime0) register, bits [3:0], for more informationonthetime-outtimer. gen general purpose timer expired 1 this bit is set when the general purpose timer expires. the time measured is the time between enabling and disabling of the timer. see the description of the scsi timer one (stime1) register, bits [3:0], for more information on the general purpose timer. hth handshake-to-handshake timer expired 0 this bit is set when the handshake-to-handshake timer expires. the time measured is the scsi request to request (target) or acknowledge-to-acknowledge (initiator) period. see the description of the scsi timer zero (stime0) register, bits [7:4], for more information on the handshake-to-handshake timer. register: 0x44 scsi longitudinal parity (slpar) read/write slpar scsi longitudinal parity [7:0] this register performs a bytewise longitudinal parity check on all scsi data received or sent through the scsi core. if one of the bytes received or sent (usually the last) is the set of correct even parity bits, slpar should go to zero (assuming it started at zero). as an example, suppose that the following three data bytes and one 7 0 slpar xxxxxxxx
4-80 registers check byte are received from the scsi bus (all signals are shown active high): a one in any bit position of the final slpar value would indicateatransmissionerror. the slpar register is also used to generate the check bytes for scsi send operations. if the slpar register contains all zeros prior to sending a block move, it contains the appropriate check byte at the end of the block move. this byte must then be sent across the scsi bus. note: writing any value to this register clears it to zero. the longitudinal parity checks are meant to provide an added measure of scsi data integrity and are entirely optional. this register does not latch scsi selection/reselection ids under any circumstances. the default value of this register is zero. the longitudinal parity function normally operates as a byte function. during 16-bit transfers, the high and low bytes are xored together and then xored into the current longitudinal parity value. by setting the slpmd bit in the scsi control two (scntl2) register, the longitudinal parity function is made to operate as a word-wide function. during 16-bit transfers, the high byte ofthescsibusisxoredwiththehighbyteofthe current longitudinal parity value, and the low byte of the scsi bus is xored with the low byte of the current longitudinal parity value. in this mode, the 16-bit longitudinal parity value is accessed a byte at a time through the scsi longitudinal parity (slpar) register. data bytes running slpar ? 00000000 1. 11001100 11001100 (xor of word 1) 2. 01010101 10011001 (xor of word 1 and 2) 3. 00001111 10010110 (xor of word 1, 2 and 3) even parity 4. 10010110 00000000
scsi registers 4-81 whichbyteisaccessediscontrolledbytheslphbenbit in the scsi control two (scntl2) register. register: 0x45 scsi wide residue (swide) read/write swide scsi wide residue [7:0] after a wide scsi data receive operation, this register contains a residual data byte if the last byte received was never sent across the dma bus. it represents either the first data byte of a subsequent data transfer, or it is a residue byte which should be cleared when an ignore wide residue message is received. it may also be an overrun data byte. the power-up value of this register is indeterminate. register: 0x46 memory access control (macntl) read/write typ chip type [7:4] these bits identify the chip type for software purposes. note: these bits no longer identify an 8xx device. these bits have been set to 0xf to indicate that the device should be uniquely identified by setting the pci configuration enable bit in the c h i p te s t tw o ( c t e s t 2 ) register and using the pci revision id and pci device id which will be shadowed in the scripts fetch selector (sfs) register. any devices that contain the value 0xf in this register should use this mechanism to uniquely identify the device. 7 0 swide xxxxxxxx 7 43210 typ dwr drd pscpt scpts 11110000
4-82 registers dwr data write 3 this bit is used to define if a data write is considered to be a local memory access. drd data read 2 this bit is used to define if a data read is considered to be a local memory access. pscpt pointer scripts 1 this bit is used to define if a pointer to a scripts indirect or table indirect fetch is considered to be a local memory access. scpts scripts 0 this bit is used to define if a scripts fetch is considered to be a local memory access. register: 0x47 general purpose pin control zero (gpcntl0) read/write this register is used to determine if the pins controlled by the general purpose (gpreg0) register are inputs or outputs. bits [4:0] in gpcntl0 correspond to bits [4:0] in the gpreg0 register. when the bits are enabled as inputs, internal pull-downs are enabled for gpio[4:2] and internal pull-ups are enabled for gpio[1:0]. the data written to each bit of the gpreg0 register is output to the appropriate gpio pin if it is set to the output mode in the gpcntl0 register. me master enable 7 the internal bus master signal is presented on gpio1 if this bit is set, regardless of the state of bit 1 (gpio1). fe fetch enable 6 the internal opcode fetch signal is presented on gpio0 if this bit is set, regardless of the state of bit 0 (gpio0). 7654 210 me fe ledc gpio gpio 00001111
scsi registers 4-83 ledc led_cntl 5 the internal connected signal (bit 3 of the interrupt status zero (istat0) register) will be presented on gpio0 if this bit is set and bit 6 of gpcntl0 is cleared and the chip is not in progress of performing an eeprom autodownload regardless of the state of bit 0 (gpio0). this provides a hardware solution to driving a scsi activity led in many implementations of lsi logic scsi chips. gpio gpio enable [4:2] general purpose control, corresponding to bits [4:2] in the gpreg0 register and pins gpio[4:2]. gpio4 powers up as a general purpose output, and gpio[3:2] power-up as general purpose inputs. gpio gpio enable [1:0] these bits power-up set, causing the gpio1 and gpio0 pins to become inputs. clearing these bits causes gpio[1:0] to become outputs. register: 0x48 scsi timer zero (stime0) read/write hth[3:0] handshake-to-handshake timer period [7:4] these bits select the handshake-to-handshake time-out period, the maximum time between scsi handshakes (sreq/ to sreq/ in target mode, or sack/ to sack/ in initiator mode). when this timing is exceeded, an interrupt is generated and the hth bit in the scsi interrupt status one (sist1) register is set. the following table contains time-out periods for the handshake-to-handshake timer, the selection/reselection timer (bits [3:0]), and the general purpose timer ( scsi timer one (stime1) bits [3:0]). for a more detailed explanation of interrupts, refer to chapter 2, ?functional description.? 7430 hth[3:0] sel[3:0] 00000000
4-84 registers sel[3:0] selection time-out [3:0] these bits select the scsi selection/reselection time-out period. when this timing (plus the 200 s selection abort time) is exceeded, the sto bit in the scsi interrupt status one (sist1) register is set. for a more detailed explanation of interrupts, refer to chapter 2, ?functional description.? hth [3:0] sel [3:0] gen [3:0] minimum time-out (80 mhz clock) with scale factor bit cleared 1 1. these values are correct if the ccf bits in the scsi control three (scntl3) register are set according to the valid combinations in the bit description. minimum time-out (80 mhz clock) with scale factor bit set 0000 disabled disabled 0001 100 s1.6ms 0010 200 s3.2ms 0011 400 s6.4ms 0100 800 s12.8ms 0101 1.6 ms 25.6 ms 0110 3.2 ms 51.2 ms 0111 6.4 ms 102.4 ms 1000 12.8 ms 204.8 ms 1001 25.6 ms 409.6 ms 1010 51.2 ms 819.2 ms 1011 102.4 ms 1.6 s 1100 204.8 ms 3.2 s 1101 409.6 ms 6.4 s 1110 819.2 ms 12.8 s 1111 1.6 + s 25.6 s
scsi registers 4-85 register: 0x49 scsi timer one (stime1) read/write r reserved 7 hthba handshake-to-handshake timer bus activity enable 6 setting this bit causes this timer to begin testing for scsi req/, ack/ activity as soon as sbsy/ is asserted, regardless of the agents participating in the transfer. gensf general purpose timer scale factor 5 setting this bit causes this timer to shift by a factor of 16. refer to the scsi timer zero (stime0) register description for details. hthsf handshake-to-handshake timer scale factor 4 setting this bit causes this timer to shift by a factor of 16. refer to the scsi timer zero (stime0) register description for details. gen[3:0] general purpose timer period [3:0] these bits select the period of the general purpose timer. the time measured is the time between enabling and disabling of the timer. when this timing is exceeded, the gen bit in the scsi interrupt status one (sist1) register is set. refer to the table under scsi timer zero (stime0) , bits [3:0], for the available time-out periods. note: to reset a timer before it expires and obtain repeatable delays, the time value must be written to zero first, and then written back to the desired value. this is also required when changing from one time value to another. 76543 0 r hthba gensf hthsf gen[3:0] x0000000
4-86 registers register: 0x4a response id zero (respid0) read/write respio0 response id zero [7:0] respid0 and response id one (respid1) contain the selection or reselection ids. in other words, these two 8-bit registers contain the id that the chip responds to on the scsi bus. each bit represents one possible id with the most significant bit of respid1 representing id 15 and the least significant bit of respid0 representing id 0. the scsi chip id (scid) register still contains the chip id used during arbitration. the chip can respond to more than one id because more than one bit can be set in the respid1 and respid0 registers. however, the chipcanarbitratewithonlyoneidvalueinthescid register. register: 0x4b response id one (respid1) read/write respid1 response id one [7:0] response id zero (respid0) and respid1 contain the selection or reselection ids. in other words, these two 8-bit registers contain the id that the chip responds to on the scsi bus. each bit represents one possible id with the most significant bit of respid1 representing id 15 and the least significant bit of respid0 representing id 0. the scsi chip id (scid) register still contains the chip id used during arbitration. the chip can respond to more than one id because more than one bit can be set in the respid1 and respid0 registers. however, the 7 0 respid0 xxxxxxxx 7 0 respid1 xxxxxxxx
scsi registers 4-87 chipcanarbitratewithonlyoneidvalueinthescid register. register: 0x4c scsi test zero (stest0) read only ssaid scsi selected as id [7:4] these bits contain the encoded value of the scsi id that the LSI53C875A is selected during a scsi selection phase. these bits work in conjunction with the response id zero (respid0) and response id one (respid1) registers, which contain the allowable ids that the LSI53C875A can respond to. during a scsi selection phase, when a valid id is put on the bus, and the LSI53C875A responds to that id, the id that the chip was selected as will be written into the ssaid[3:0] bits. slt selection response logic test 3 this bit is set when the LSI53C875A is ready to be selected or reselected. this does not take into account the bus settle delay of 400 ns. this bit is used for functional test and fault purposes. art arbitration priority encoder test 2 this bit is always set when the LSI53C875A exhibits the highest priority id asserted on the scsi bus during arbitration. it is primarily used for chip level testing, but it maybeusedduringlowlevelmodeoperationto determine if the LSI53C875A won arbitration. soz scsi synchronous offset zero 1 this bit indicates that the current synchronous sreq/, sack/ offset is zero. this bit is not latched and may change at any time. it is used in low level synchronous scsi operations. when this bit is set, the LSI53C875A functioning as an initiator, is waiting for the target to request data transfers. if the LSI53C875A is a target, then the initiator has sent the offset number of acknowledges. 7 43210 ssaid slt art soz som xxxx0x11
4-88 registers som scsi synchronous offset maximum 0 this bit indicates that the current synchronous sreq/, sack/ offset is the maximum specified by bits [3:0] in the scsi transfer (sxfer) register. this bit is not latched and may change at any time. it is used in low level synchronous scsi operations. when this bit is set, the LSI53C875A, as a target, is waiting for the initiator to acknowledge the data transfers. if the LSI53C875A is an initiator, then the target has sent the offset number of requests. register: 0x4d scsi test one (stest1) read/write sclk scsi clock 7 when set, this bit disables the external sclk (scsi clock) pin, and the chip uses the pci clock as the internal scsi clock. when set, it will also select the pci clock as the internal scsi clock if the internal clock quadrupler is enabled and selected. iso scsi isolation mode 6 this bit allows the LSI53C875A to put the scsi bidirectional and input pins into a low power mode when the scsi bus is not in use. when this bit is set, the scsi bus inputs are logically isolated from the scsi bus. r reserved [5:4] qen sclk quadrupler enable 3 this bit, when set, powers up the internal clock quadrupler circuit, which quadruples the sclk. a 40 mhz clock is quadrupled to an internal 160 mhz scsi clock, as required for ultra scsi operation. the output from a 20 mhz sclk is 80 mhz. when cleared, this bit powers down the internal quadrupler circuit. 76543210 sclk iso rqenqsel r 00 x x00 x x
scsi registers 4-89 qsel sclk quadrupler select 2 this bit, when set, selects the output of the internal clock quadrupler for use as the internal scsi clock. when cleared, this bit selects the clock presented on sclk for use as the internal scsi clock. r reserved [1:0] register: 0x4e scsi test two (stest2) read/write sce scsi control enable 7 setting this bit allows assertion of all scsi control and data lines through the scsi output control latch (socl) and scsi output data latch (sodl) registers regardless of whether the LSI53C875A is configured as a target or initiator. note: do not set this bit during normal operation, since it could cause contention on the scsi bus. it is included for diagnostic purposes only. rof reset scsi offset 6 setting this bit clears any outstanding synchronous sreq/sack offset. set this bit if a scsi gross error condition occurs and to clear the offset when a synchronous transfer does not complete successfully. the bit automatically clears itself after resetting the synchronous offset. r reserved 5 this bit must be cleared. slb scsi loopback mode 4 setting this bit allows the LSI53C875A to perform scsi loopback diagnostics. that is, it enables the scsi core to simultaneously perform as both the initiator and the target. 76543210 sce rof r slb szm aws ext low 00 000000
4-90 registers szm scsi high impedance mode 3 setting this bit places all the open drain 48 ma scsi drivers into a high impedance state. this is to allow internal loopback mode operation without affecting the scsi bus. aws alwayswidescsi 2 when this bit is set, all scsi information transfers are done in 16-bit wide mode. this includes data, message, command, status and reserved phases. normally, deassert this bit since 16-bit wide message, command, and status phases are not supported by the scsi specifications. ext extend sreq/sack/ filtering 1 lsi logic tolerant scsi receiver technology includes a special digital filter on the sreq/ and sack/ pins which causes the disregarding of glitches on deasserting edges. setting this bit increases the filtering period from 30 ns to 60 ns on the deasserting edge of the sreq/ and sack/ signals. note: never set this bit during fast scsi (greater than 5 mbyte transfers per second) operations, because a valid assertion could be treated as a glitch. low scsi low level mode 0 setting this bit places the LSI53C875A in the low level mode. in this mode, no dma operations occur, and no scripts execute. arbitration and selection may be performed by setting the start sequence bit as described in the scsi control zero (scntl0) register. scsi bus transfers are performed by manually asserting and polling scsi signals. clearing this bit allows instructions to be executed in scsi scripts mode. note: it is not necessary to set this bit for access to the scsi bit-level registers scsi output data latch (sodl) , scsi bus control lines (sbcl) , and input registers.
scsi registers 4-91 register: 0x4f scsi test three (stest3) read/write te tolerant enable 7 setting this bit enables the active negation portion of lsi logic tolerant technology. active negation causes the scsi request, acknowledge, data, and parity signals to be actively deasserted, instead of relying on external pull-ups, when the LSI53C875A is driving these signals. active deassertion of these signals occurs only when the LSI53C875A is in an information transfer phase. when operating in a differential environment or at fast scsi timings, tolerant active negation should be enabled to improve setup and deassertion times. active negation is disabled after reset or when this bit is cleared. for more information on lsi logic tolerant technology, see chapter 1, ?general description.? note: set this bit if the enable ultra scsi bit in scsi control three (scntl3) is set. str scsi fifo test read 6 setting this bit places the scsi core into a test mode in which the scsi fifo is easily read. reading the least significant byte of the scsi output data latch (sodl) register causes the fifo to unload. the functions are summarized in the table below. hsc halt scsi clock 5 asserting this bit causes the internal divided scsi clock to come to a stop in a glitchless manner. this bit is used 76543210 te str hsc dsi s16 ttm csf stw 0000x000 register name register operation fifo bits fifo function sodl read [15:0] unload sodl0 read [7:0] unload sodl1 read [15:8] none
4-92 registers for test purposes or to lower i dd during a power-down mode. dsi disable single initiator response 4 if this bit is set, the LSI53C875A ignores all bus-initiated selection attempts that employ the single initiator option from scsi-1. in order to select the LSI53C875A while this bit is set, the LSI53C875A?s scsi id and the initiator?s scsi id must both be asserted. assert this bit in scsi-2 systems so that a single bit error on the scsi bus is not interpreted as a single initiator response. s16 16-bit system 3 if this bit is set, all devices in the scsi system implementation are assumed to be 16-bit. this causes the LSI53C875A to always check the parity bit for scsi ids [15:8] during bus-initiated selection or reselection, assuming parity checking has been enabled. if an 8-bit scsi device attempts to select the LSI53C875A while this bit is set, the LSI53C875A will ignore the selection attempt. this is because the parity bit for ids [15:8] will not be driven. see the description of the enable parity checking bit in the scsi control zero (scntl0) register for more information. ttm timer test mode 2 asserting this bit facilitates testing of the selection time-out, general purpose, and handshake-to-handshake timers by greatly reducing all three time-out periods. setting this bit starts all three timers and if the respective bits in the scsi interrupt enable one (sien1) register are asserted, the LSI53C875A generates interrupts at time-out. this bit is intended for internal manufacturing diagnosis and should not be used. csf clear scsi fifo 1 setting this bit causes the ?full flags? for the scsi fifo to be cleared. this empties the fifo. this bit is self-clearing. in addition to the scsi fifo pointers, the scsi input data latch (sidl) , scsi output data latch (sodl) , and (sodr, a hidden buffer register which is not accessible) full bits in the scsi status zero (sstat0) and scsi status two (sstat2) are cleared.
scsi registers 4-93 stw scsi fifo test write 0 setting this bit places the scsi core into a test mode in which the fifo is easily read or written. while this bit is set, writes to the least significant byte of the scsi output data latch (sodl) register cause the entire word contained in the sodl to be loaded into the fifo. these functions are summarized in the table below. registers: 0x50?0x51 scsi input data latch (sidl) read only sidl scsi input data latch [15:0] this register is used primarily for diagnostic testing, programmed i/o operation, or error recovery. data receivedfromthescsibuscanbereadfromthis register. data can be written to the scsi output data latch (sodl) register and then read back into the LSI53C875A by reading this register to allow loopback testing. when receiving scsi data, the data flows into this register and out to the host fifo. this register differs from the scsi bus data lines (sbdl) register; sidl contains latched data and the sbdl always contains exactly what is currently on the scsi data bus. reading this register causes the scsi parity bit to be checked, and causes a parity error interrupt if the data is not valid. the power-up values are indeterminate. register name register operation fifo bits fifo function sodl write [15:0] load sodl0 write [7:0] load sodl1 write [15:8] none 15 0 sidl xxxx x x x x x xxx x xxx
4-94 registers register: 0x52 scsi test four (stest4) read only r reserved [7:6] lock frequency lock 5 this bit is used when enabling the scsi clock quadrupler, which allows the LSI53C875A to transfer data at ultra scsi rates. poll this bit for a 1 to determine that the clock quadrupler has locked. for more information on enabling the clock quadrupler, refer to the descriptions of scsi te s t o n e ( s t e s t 1 ) ,bits2and3. r reserved [4:0] register: 0x53 reserved registers: 0x54?0x55 scsi output data latch (sodl) read/write sodl scsi output data latch [15:0] this register is used primarily for diagnostic testing or programmed i/o operation. data written to this register is asserted onto the scsi data bus by setting the assert data bus bit in the scsi control one (scntl1) register. this register is used to send data using programmed i/o. data flows through this register when sending data in any mode. it is also used to write to the synchronous data fifo when testing the chip. the power-up value of this register is indeterminate. 7654 0 rlock r x x0 x x x x x 15 0 sodl xxxx x x x x x xxx x xxx
scsi registers 4-95 register: 0x56 chip control 0 (ccntl0) read/write enpmj enable phase mismatch jump 7 upon setting this bit, any phase mismatches do not interrupt but force a jump to an alternate location to handle the phase mismatch. prior to actually taking the jump, the appropriate remaining byte counts and addresses will be calculated such that they can be easily stored to the appropriate memory location with scripts store instruction. in the case of a scsi send, any data in the part will be automatically cleared after being accounted for. in the case of a scsi receive, all data will be flushed out of the part and accounted for prior to taking the jump. this feature does not cover, however, the byte that may appear in scsi wide residue (swide) . this byte must be flushed manually. this bit also enables the flushing mechanism to flush dataduringadata-inphasemismatchinamoreefficient manner. pmjctl jump control 6 this bit controls which decision mechanism is used when jumpingonphasemismatch.whenthisbitisclearedthe LSI53C875A will use phase mismatch jump address 1 (pmjad1) when the wsr bit is cleared and phasemismatchjumpaddress2(pmjad2) when the wsr bit is set. when this bit is set the LSI53C875A will use jump address one (pmjad1) on data out (data out, command, message out) transfers and jump address two (pmjad2) on data in (data in, status, message in) transfers. note that the phase referred to here is the phase encoded in the block move scripts instruction, not the phase on the scsi bus that caused the phase mismatch. 76543210 enpmj pmjctl enndj disfc rdils r 0000 x x0 x
4-96 registers enndj enable jump on nondata phase mismatches 5 this bit controls whether or not a jump is taken during a nondata phase mismatch (i.e. message in, message out, status, or command). when this bit is clear, jumps will only be taken on data-in or data-out phases and a phase mismatch interrupt will be generated for all other phases. when this bit is set, jumps will be taken regardless of the phase in the block move. note that the phase referred to here is the phase encoded in the block move scripts instruction, not the phase on the scsi bus that caused the phase mismatch. disfc disable auto fifo clear 4 this bit controls whether or not the fifo is automatically cleared during a data-out phase mismatch. when set, data in the dma fifo as well as data in the scsi output data latch (sodl) and sodr, a hidden buffer register which is not accessible, will not be cleared after calculations on them are complete. when cleared, the dma fifo and sodl and sodr will automatically be cleared. this bit also disables the enhanced flushing mechanism. r reserved [3:2] dils disable internal load and store 1 this bit controls whether or not load and store data transfers in which the source/destination is located in scripts ram generate external pci cycles. if cleared, load and store data transfers of this type will not generate pci cycles, but will stay internal to the chip. if set, load and store data transfers of this type will generate pci cycles. r reserved 0
scsi registers 4-97 register: 0x57 chip control 1 (ccntl1) read/write zmode high impedance mode 7 setting this bit causes the LSI53C875A to place all output and bidirectional pins except mac/_testout, into a high impedance state. also, setting this bit causes all i/o pins to become inputs, and all pull-ups and pull-downs to be disabled. when this bit is set, the mac/_testout pin becomes the output pin for the connectivity test of the LSI53C875A signals in the ?and-tree? test mode. in order to read data out of the LSI53C875A, this bit must be cleared. this bit is intended for board-level testing only. do not set this bit during normal system operation. r reserved [6:4] ddac disable dual address cycle 3 when this bit is set, all 64-bit addressing as a master will be disabled. no dual address cycles will be generated by the LSI53C875A. when this bit is cleared, the LSI53C875A will generate dual address cycles based on the master operation being performed and the value of its associated selector register. 64timod 64-bit table indirect indexing mode 2 when this bit is cleared, bits [24:28] of the first table entry dword will select one of 22 possible selectors to be used in a bmov operation. when this bit is set, bits [24:31] of the first table entry dword will be copied directly into dnad64 to provide 40-bit addressing capability. this bit will only function if the en64tibmv bit is set. index mode 0 (64timod clear) table entry format: 76 43 2 1 0 zmode r ddac 64timod en64tibmv en64dbmv 0 x x x0 0 0 0 [31:29] [28:24] [23:0] reserved sel index byte count source/destination address [31:0]
4-98 registers index mode 1 (64timod set) table entry format: en64tibmv enable 64-bit table indirect bmov 1 setting this bit enables 64-bit addressing for table indirect bmovs using the upper byte (bit [24:31]) of the first dword of the table entry. when this bit is cleared table indirect bmovs will use the static block move selector (sbms) register to obtain the upper 32 bits of the data address. en64dbmv enable 64-bit direct bmov 0 setting this bit enables the 64-bit version of a direct bmov. when this bit is cleared direct bmovs will use the static block move selector (sbms) register to obtain the upper 32 bits of the data address. registers: 0x58?0x59 scsi bus data lines (sbdl) read only sbdl scsi bus data lines [15:0] this register contains the scsi data bus status. even though the scsi data bus is active low, these bits are active high. the signal status is not latched and is a true representation of exactly what is on the data bus at the time the register is read. this register is used when receiving data using programmed i/o. this register can also be used for diagnostic testing or in low level mode. the power-up value of this register is indeterminate. if the chip is in the wide mode ( scsi control three (scntl3) ,bit3and s c s i te s t tw o ( s t e s t 2 ) ,bit2are set) and sbdl is read, both byte lanes are checked for parity regardless of phase. when in a nondata phase, this will cause a parity error interrupt to be generated because the upper byte lane parity is invalid. [31:24] [23:0] src/dest addr [39:32] byte count source/destination address [31:0] 15 0 sbdl xxxx x x x x x xxx x xxx
64-bit scripts selectors 4-99 register: 0x5a?0x5b reserved registers: 0x5c?0x5f scratch register b (scratchb) read/write scratchb scratch register b [31:0] this is a general purpose user definable scratch pad register. apart from cpu access, only register read/write and memory moves directed at the scratch register will alter its contents. the power-up values are indeterminate. a special mode of this register can be enabled by setting the pci configuration into enable bit in the c h i p te s t tw o ( c t e s t 2 ) register. if this bit is set, the scratch b register returns bits [31:12] of the scripts ram pci base address register two (scripts ram) in bits [31:12] of the scratch b register when read. when read, bits [11:0] of scratch b will always return zeros in this mode. writes to the scratch b register are unaffected. resetting the pci configuration into enable bit causes the scratch b register to return to normal operation. registers: 0x60?0x9f scratch registers c?r (scratchc?scratchr) read/write these are general purpose user definable scratch pad registers. apart from cpu access, only register read/write, memory moves and load and stores directed at a scratch register will alter its contents. the power-up values are indeterminate. 4.3 64-bit scripts selectors the following registers are used to hold the upper 32-bit addresses for various scripts operations. when a particular type of scripts 31 0 scratchb xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
4-100 registers operation is performed, one of the six selector registers below will be used to generate a 64-bit address. if the selector for a particular device operation is zero, then a standard 32-bit address cycle will be generated. if the selector value is nonzero, then a dac will be issued and the 64-bit address will be presented in two address phases. all selectors default to 0 (zero) with the exception of the 16 scratch registers, these power-up in an indeterminate state and should be initialized before they are used. all selectors can be read/written using the load and store scripts instruction, memory-to-memory move, read/write scripts instruction, or cpu with scripts not running. note: crossing of selector boundaries in one memory operation is not supported. registers: 0xa0?0xa3 memory move read selector (mmrs) read/write mmrs memory move read selector (mmrs) supplies the upper dword of a 64-bit address during data read operations for memory-to-memory moves and absolute address load operations. a special mode of this register can be enabled by setting the pci configuration enable bit in the c h i p te s t tw o (ctest2) register. because the LSI53C875A supports only a 32-bit memory mapped pci base address, the mmrs register is always read as 0x00000000 when in the special mode. writes to the mmrs register are unaffected. clearing the pci configuration into enable bit causes the mmrs register to return to normal operation. 31 0 mmrs 00000000000000000000000000000000
64-bit scripts selectors 4-101 registers: 0xa4?0xa7 memory move write selector (mmws) read/write mmws memory move write selector [31:0] supplies the upper dword of a 64-bit address during data write operations during memory-to-memory moves and absolute address store operations. a special mode of this register can be enabled by setting the pci configuration into enable bit in the chip test two (ctest2) register. because the LSI53C875A supports only a 32-bit scripts ram pci base address, the mmws register is always read as 0x00000000 when in the special mode. writes to the mmws register are unaffected. clearing the pci configuration enable bit causes the mmws register to return to normal operation. registers: 0xa8?0xab scripts fetch selector (sfs) read/write sfs scripts fetch selector [31:0] supplies the upper dword of a 64-bit address during scripts fetches and indirect fetches (excluding table indirect fetches). this register can be loaded automatically using a 64-bit jump instruction. a special mode of this register can be enabled by setting the pci configuration into enable bit in the chip test two (ctest2) register. if this bit is set, bits [23:16] of the sfs register return the pci revision id (rev id) register value and bits [15:0] return the pci device id register value when read. 31 0 mmws 00000000000000000000000000000000 31 0 sfs 00000000000000000000000000000000
4-102 registers writes to the sfs register are unaffected. clearing the pci configuration into enable bit causes the sfs register to return to normal operation. registers: 0xac?0xaf dsa relative selector (drs) read/write drs dsa relative selector [31:0] supplies the upper dword of a 64-bit address during table indirect fetches and load and store data structure address (dsa) relative operations. registers: 0xb0?0xb3 staticblockmoveselector(sbms) read/write sbms static block move selector [31:0] supplies the upper dword of a 64-bit address during block move operations, reads or writes. this register is static and will not be changed when a 64-bit direct bmov is used. 31 0 drs 00000000000000000000000000000000 31 0 sbms 00000000000000000000000000000000
phase mismatch jump registers 4-103 registers: 0xb4?0xb7 dynamic block move selector (dbms) read/write dbms dynamic block move selector [31:0] supplies the upper dword of a 64-bit address during block move operations, reads or writes. this register is used only during 64-bit direct bmov instructions and will be reloaded with the upper 32-bit data address upon execution of a 64-bit direct bmovs. registers: 0xb8?0xbb dma next address 64 (dnad64) read/write dnad64 dma next address 64 [31:0] this register holds the current selector being used in a given host transaction. the appropriate selector is copied to this register prior to beginning a host transaction. registers: 0xbc?0xbf reserved 4.4 phase mismatch jump registers eight 32-bit registers contain the byte count and addressing information required to update the direct, indirect, or table indirect bmov instructions with new byte counts and addresses. the eight register descriptions follow. all registers can be read/written using the load and store scripts instructions, memory-to-memory moves, read/write scripts instructions, or the cpu with scripts not running. 31 0 dbms 00000000000000000000000000000000 31 0 dnad64 00000000000000000000000000000000
4-104 registers registers: 0xc0?0xc3 phasemismatchjumpaddress1(pmjad1) read/write pmjad1 phase mismatch jump address 1 [31:0] this register contains the 32-bit address that will be jumped to upon a phase mismatch. depending upon the state of the pmjctl bit in register chip control 0 (ccntl0) this address will either be used during an outbound (data out, command, message out) phase mismatch (pmjctl = 0) or when the wsr bit is cleared (pmjctl = 1). it should be loaded with an address of a scripts routine that will handle the updating of memory data structures of the bmov that was executing when the phase mismatch occurred. registers: 0xc4?0xc7 phasemismatchjumpaddress2(pmjad2) read/write pmjad2 phase mismatch jump address 2 [31:0] this register contains the 32-bit address that will be jumped to upon a phase mismatch. depending upon the state of the pmjctl bit in register chip control 0 (ccntl0) this address will either be used during an inbound (data in, status, message in) phase mismatch (pmjctl = 0) or when the wsr bit is set (pmjctl = 1). it should be loaded with an address of a scripts routine that will handle the updating of memory data structures of the bmov that was executing when the phase mismatch occurred. 31 0 pmjad1 00000000000000000000000000000000 31 0 pmjad2 00000000000000000000000000000000
phase mismatch jump registers 4-105 registers: 0xc8?0xcb remaining byte count (rbc) read/write rbc remaining byte count (rbc) [31:0] this register contains the byte count that remains for the bmov that was executing when the phase mismatch occurred. in the case of direct or indirect bmov instructions, the upper byte of this register will also contain the opcode of the bmov that was executing. in the case of a table indirect bmov instruction, the upper byte will contain the upper byte of the table indirect entry that was fetched. in the case of a scsi data receive, this byte count will reflect all data received from the scsi bus, including any byte in scsi wide residue (swide) . there will be no data remaining in the part that must be flushed to memorywiththeexceptionofapossiblebyteinthe swide register. that byte must be flushed to memory manually in scripts. in the case of a scsi data send, this byte count will reflect all data sent out onto the scsi bus. any data left in the part from the phase mismatch will be ignored and automatically cleared from the fifos. registers: 0xcc?0xcf updated address (ua) read/write ua updated address [31:0] this register will contain the updated data address for the bmov that was executing when the phase mismatch occurred. 31 0 rbc 00000000000000000000000000000000 31 0 ua 00000000000000000000000000000000
4-106 registers in the case of a scsi data receive, if there is a byte in the scsi wide residue (swide) register then this address will point to the location where that byte must be stored. the swide byte must be manually written to memory and this address must be incremented prior to updating any scatter/gather entry. in the case of a scsi data receive, if there is not a byte in the swide register then this address will be the next location that should be written to when this i/o restarts. no manual flushing will be necessary. in the case of a scsi data send, all data sent to the scsi bus will be accounted for and any data left in the part will be ignored and will be automatically cleared from the fifos. registers: 0xd0?0xd3 entry storage address (esa) read/write this register's value depends on the type of bmov being executed. the three types of bmovs are listed below. esa entry storage address [31:0] this register's value depends on the type of bmov being executed. the three types of bmovs are listed below. 31 0 esa 00000000000000000000000000000000 direct bmov: in the case of a direct bmov, this register will contain the address the bmov was fetched from when the phase mismatch occurred. indirect bmov: in the case of an indirect bmov, this register will contain the address the bmov was fetched from when the phase mismatch occurred. table indirect bmov: in the case of a table indirect bmov, this register will contain the address of the table indirect entry being used when the phase mismatch occurred.
phase mismatch jump registers 4-107 registers: 0xd4?0xd7 instruction address (ia) read/write ia instruction address [31:0] this register always contains the address of the bmov instruction that was executing when the phase mismatch occurred. this value will always match the value in the entry storage address (esa) except in the case of a table indirect bmov in which case the esa will have the address of the table indirect entry and this register will point to the address of the bmov instruction. registers: 0xd8?0xda scsi byte count (sbc) read only sbc scsi byte count [23:0] this register contains the count of the number of bytes transferred to or from the scsi bus during any given bmov. this value is used in calculating the information placed into the remaining byte count (rbc) and updated address (ua) register and should not need to be used in normal operations. there are two conditions in which this byte count will not match the number of bytes transferred exactly. if a bmov is executed to transfer an odd number of bytes across a wide bus then the byte count at the end of the bmov will be greater than the number of bytes sent by one. this will also happen in an odd byte count wide receive case. also, in the case of a wide send in which there is a chain byte from a previous transfer, the count will not reflect the chain byte sent across the bus during that bmov. the reason for this is due to the fact that to determine the correct address to start fetching data from after a phase mismatch this byte 31 0 ia 00000000000000000000000000000000 23 0 sbc 000000000000000000000000
4-108 registers cannot be counted for this bmov as it was actually part of the byte count for the previous bmov. register: 0xdb reserved registers: 0xdc?0xdf cumulative scsi byte count (csbc) read/write csbc cumulative scsi byte count [31:0] this loadable register contains a cumulative count of the actual number of bytes that have been transferred across the scsi bus during data phases, i.e. it will not count bytes sent in command, status, message in or message out phases. it will count bytes as long as the phase mismatch enable (enpmj) bit in the chip control 0 (ccntl0) register is set. unlike the scsi byte count (sbc) this count will not be cleared on each bmov instruction but will continue to count across multiple bmov instructions. this register can be loaded with any arbitrary start value. registers: 0xe0?0xff reserved 31 0 csbc 00000000000000000000000000000000
LSI53C875A pci to ultra scsi controller 5-1 chapter 5 scsi scripts instruction set the LSI53C875A contains a scsi scripts processor that permits both dma and scsi commands to be fetched from host memory or internal scripts ram. algorithms written in scsi scripts control the actions of the scsi and dma cores. the scripts processor executes complex scsi bus sequences independently of the host cpu. this chapter describes the scsi scripts instruction set used to write these algorithms. the following sections describe the benefits and use of scsi scripts instructions. ? section 5.1, ?low level register interface mode? ? section 5.2, ?high level scsi scripts mode? ? section 5.3, ?block move instruction? ? section 5.4, ?i/o instruction? ? section 5.5, ?read/write instructions? ? section 5.6, ?transfer control instructions? ? section 5.7, ?memory move instructions? ? section 5.8, ?load and store instructions? after power-up and initialization, the LSI53C875A can be operated in the low level register interface mode or in the high level scsi scripts mode. 5.1 low level register interface mode with the low level register interface mode, the user has access to the dma control logic and the scsi bus control logic. an external processor has access to the scsi bus signals and the low level dma signals, which allows creation of complicated board level test algorithms. the low level interface is useful for backward compatibility with scsi devices that
5-2 scsi scripts instruction set require certain unique timings or bus sequences to operate properly. another feature allowed at the low level is loopback testing. in loopback mode,thescsicorecanbedirectedtotalktothedmacoretotest internal data paths all the way out to the chip?s pins. 5.2 high level scsi scripts mode to operate in the scsi scripts mode, the LSI53C875A requires only a scripts start address. the start address must be at a dword (four byte) boundary. this aligns subsequent scripts at a dword boundary since all scripts are 8 or 12 bytes long. instructions are fetched until an interrupt instruction is encountered, or until an unexpected event (such as a hardware error) causes an interrupt to the external processor. once an interrupt is generated, the LSI53C875A halts all operations until the interrupt is serviced. then, the start address of the next scripts instruction may be written to the dma scripts pointer (dsp) register to restart the automatic fetching and execution of instructions. the scsi scripts mode of execution allows the LSI53C875A to make decisions based on the status of the scsi bus, which offloads the microprocessor from servicing the numerous interrupts inherent in i/o operations. given the rich set of scsi oriented features included in the instruction set, and the ability to re-enter the scsi algorithm at any point, this high level interface is all that is required for both normal and exception conditions. switching to low level mode for error recovery should never be required. the following types of scripts instructions are implemented in the LSI53C875A, as shown in ta b l e 5 . 1 :
high level scsi scripts mode 5-3 each instruction consists of two or three 32-bit words. the first 32-bit word is always loaded into the dma command (dcmd) and dma byte counter (dbc) registers, the second into the dma scripts pointer save (dsps) register. the third word, used only by memory move instructions, is loaded into the temporary (temp) shadow register. in an indirect i/o or move instruction, the first two 32-bit opcode fetches is followed by one or two more 32-bit fetch cycles. 5.2.1 sample operation this sample operation describes execution of a scripts instruction for a block move instruction. ? the host cpu, through programmed i/o, gives the dma scripts pointer (dsp) register (in the operating register file) the starting address in main memory that points to a scsi scripts program for execution. ? loading the dma scripts pointer (dsp) register causes the LSI53C875A to fetch its first instruction at the address just loaded. this is from main memory or the internal ram, depending on the address. table 5.1 scripts instructions instruction description block move block move instruction moves data between the scsi bus and memory. i/o or read/write i/o or read/write instructions cause the LSI53C875A to trigger common scsi hardware sequences, or to move registers. transfer control transfer control instruction allows scripts instructions to make decisions based on real time scsi bus conditions. memory move memory move instruction causes the LSI53C875A to execute block moves between different parts of main memory. load and store load and store instructions provide a more efficient way to move data to/from memory from/to an internal register in the chip without using the memory move instruction.
5-4 scsi scripts instruction set ? the LSI53C875A typically fetches two dwords (64 bits) and decodes the high order byte of the first longword as a scripts instruction. if the instruction is a block move, the lower three bytes of the first longword are stored and interpreted as the number of bytes to be moved. the second longword is stored and interpreted as the 32-bit beginning address in main memory to which the move is directed. ? for a scsi send operation, the LSI53C875A waits until there is enough space in the dma fifo to transfer a programmable size block of data. for a scsi receive operation, it waits until enough data is collected in the dma fifo for transfer to memory. at this point, the LSI53C875A requests use of the pci bus again to transfer the data. ? when the LSI53C875A is granted the pci bus, it executes (as a bus master) a burst transfer (programmable size) of data, decrement the internally stored remaining byte count, increment the address pointer, and then release the pci bus. the LSI53C875A stays off the pci bus until the fifo can again hold (for a write) or has collected (for a read) enough data to repeat the process. the process repeats until the internally stored byte count has reached zero. the LSI53C875A releases the pci bus and then performs another scripts instruction fetch cycle, using the incremented stored address maintained in the dma scripts pointer (dsp) register. execution of scripts instructions continues until an error condition occurs or an interrupt scripts instruction is received. at this point, the LSI53C875A interrupts the host cpu and waits for further servicing by the host system. it can execute independent block move instructions specifying new byte counts and starting locations in main memory. in this manner, the LSI53C875A performs scatter/gather operations on data without requiring help from the host program, generating a host interrupt, or requiring an external dma controller to be programmed. an overview of this process is presented in figure 5.1 .
high level scsi scripts mode 5-5 figure 5.1 scripts overview system processor system memory scsi initiator write example select atn 0, alt_addr move from identify_msg_buf, when msg_out move from data_buf when data_out move from stat_in_buf, when status move scntl2 & 7f to scntl2 clear ack wail disconnect alt2 int 10 ta b l e byte count address byte count address byte count address byte count address data structure message buffer command buffer data buffer status buffer b u s s y s t e m write dsa write dsp fetch scripts data LSI53C875A scsi bus see block diagram in chapter 2 for details, p c i
5-6 scsi scripts instruction set 5.3 block move instruction performing a block move instruction, bit 5, source i/o - memory enable (siom) and bit 4, destination i/o - memory enable (diom) in the dma mode (dmode) register determines whether the source/destination address resides in memory or i/o space. when data is being moved onto the scsi bus, siom controls whether that data comes from i/o or memory space. when data is being moved off of the scsi bus, diom controls whether that data goes to i/o or memory space. 5.3.1 first dword it[1:0] instruction type - block move [31:30] the it bit configuration (00) defines a block move instruction type. ia indirect addressing 29 this bit determines if addressing is direct or indirect. if ia bit is (0), use destination field as an address (direct addressing). if ia bit is (1), use destination field as a pointer to an address (indirect addressing). when this bit is zero, user data is moved to or from the 32-bit data start address for the block move instruction. the value is loaded into the chip?s address register and incremented as data is transferred. the address of the data to move is in the second dword of this instruction. when this bit is one, the 32-bit user data start address for the block move is the address of a pointer to the actual data buffer address. the value at the 32-bit start address is loaded into the chip?s dma next address (dnad) register using a third longword fetch (4-byte transfer across the host computer bus). 31 30 29 28 27 26 24 23 0 dma command (dcmd) register dma byte counter (dbc) register it[1:0] ia tia opc scsip[2:0] transfer counter [23:0] 0 0 x x x x x x xxxxxxxxxxxxxxxxxxxxxxxx
block move instruction 5-7 direct addressing the byte count and absolute address are: indirect addressing use the fetched byte count, but fetch the data address from the address in the instruction. once the data pointer address is loaded, it is executed as when the chip operates in the direct mode. this indirect feature allows a table of data buffer addresses to be specified. using the scsi scripts assembler, the table offset is placed in the script at compile time. then at the actual data transfer time, the offsets are added to the base address of the data address table by the external processor. the logical i/o driver builds a structure of addresses for an i/o rather than treating each address individually. this feature makes it possible to locate scsi scripts in a prom. note: do not use indirect and table indirect addressing simultaneously; use only one addressing method at a time. tia table indirect 28 32-bit addressing when this bit is set, the 24-bit signed value in the start address of the move is treated as a relative displacement from the value in the data structure address (dsa) register. both the transfer count and the source/ destination address are fetched from this location. use the signed integer offset in bits [23:0] of the second four bytes of the instruction, added to the value in the data structure address (dsa) register, to fetch first the byte count and then the data address. the signed value is combined with the data structure base address to generate the physical address used to fetch values from command byte count address of data command byte count address of pointer to data
5-8 scsi scripts instruction set the data structure. sign extended values of all ones for negative values are allowed, but bits [31:24] are ignored. note: do not use indirect and table indirect addressing simultaneously; use only one addressing method at a time. priortothestartofani/o,the data structure address (dsa) register should be loaded with the base address of the i/o data structure. the address may be any address on a longword boundary. after a table indirect opcode is fetched, the dsa is added to the 24-bit signed offset value from the opcode to generate the address of the required data; both positive and negative offsets are allowed. a subsequent fetch from that address brings the data values into the chip. for a move instruction, the 24-bit byte count is fetched from system memory. then the 32-bit physical address is brought into the LSI53C875A. execution of the move begins at this point. scripts can directly execute operating system i/o data structures, saving time at the beginning of an i/o operation. the i/o data structure can begin on any longword boundary and may cross system segment boundaries. there are two restrictions on the placement of pointer data in system memory: ? the eight bytes of data in the move instruction must be contiguous, as shown below, and ? indirect data fetches are not available during execution of a memory-to-memory dma operation. command not used don?t care table offset 00 byte count physical data address
block move instruction 5-9 opc opcode 27 this 1-bit opcode field defines the type of block move (move) instruction to be preformed in target and initiator mode. target mode in target mode, the opcode bit defines the following operations: these instructions perform the following steps: 1. the LSI53C875A verifies that it is connected to the scsi bus as a target before executing this instruction. 2. the LSI53C875A asserts the scsi phase signals (smsg/, sc_d/,andsi_o/)asdefinedbythephasefieldbitsinthe instruction. 3. if the instruction is for the command phase, the LSI53C875A receives the first command byte and decodes its scsi group code. ? if the scsi group code is either group 0, group 1, group 2, or group 5, and if the vendor unique enhancement 1 (vue1) bit (scntl2 bit 1) is clear, then the LSI53C875A overwrites the dma byte counter (dbc) register with the length of the command descriptor block: 6, 10, or 12 bytes. ? if the vendor unique enhancement 1 (vue1) bit (scntl2 bit 1) is set, the LSI53C875A receives the number of bytes in the byte count regardless of the group code. ? if the vendor unique enhancement 1 bit is clear and group code is vendor unique, the LSI53C875A receives the number of bytes in the count. ? if any other group code is received, the dma byte counter (dbc) register is not modified and the LSI53C875A requests the number of bytes specified in the dma byte counter (dbc) register. if the dbc opc instruction defined 0 move/move64 1 chmov/chmov64
5-10 scsi scripts instruction set register contains 0x000000, an illegal instruction interrupt is generated. 4. the LSI53C875A transfers the number of bytes specified in the dbc register starting at the address specified in the dma next address (dnad) register. if the opcode bit is set and a data transfer ends on an odd byte boundary, the LSI53C875A stores the last byte in the scsi wide residue (swide) register during a receive operation. this byte is combined with the first byte from the subsequent transfer so that a wide transfer can be completed. 5. if the satn/ signal is asserted by the initiator or a parity error occurred during the transfer, the transfer can optionally be halted and an interrupt generated. the disable halt on parity error or atn bit in the scsi control one (scntl1) register controls whether the LSI53C875A halts on these conditions immediately, or waits until completion of the current move. initiator mode in target mode, the opcode bit defines the following operations: these instructions perform the following steps: 1. the LSI53C875A verifies that it is connected to the scsi bus as an initiator before executing this instruction. 2. the LSI53C875A waits for an unserviced phase to occur. an unserviced phase is any phase (with sreq/ asserted) for which the LSI53C875A has not yet transferred data by responding with a sack/. 3. the LSI53C875A compares the scsi phase bits in the dma command (dcmd) register with the latched scsi phase lines stored in the scsi status one (sstat1) opc instruction defined 0chmov 1move
block move instruction 5-11 register. these phase lines are latched when sreq/ is asserted. 4. ifthescsiphasebitsmatchthevaluestoredinthescsi scsi status one (sstat1) register, the LSI53C875A transfers the number of bytes specified in the dma byte counter (dbc) register starting at the address pointed to by the dma next address (dnad) register. if the opcode bit is cleared and a data transfer ends on an odd byte boundary, the LSI53C875A stores the last byte in the scsi wide residue (swide) register during a receive operation, or in the scsi output data latch (sodl) register during a send operation. this byte is combined with the first byte from the subsequent transfer so that a wide transfer can complete. 5. if the scsi phase bits do not match the value stored in the scsi status one (sstat1) register, the LSI53C875A generates a phase mismatch interrupt and the instruction is not executed. 6. during a message-out phase, after the LSI53C875A has performed a select with attention (or satn/ is manually asserted with a set atn instruction), the LSI53C875A deasserts satn/ during the final sreq/sack/ handshake. 7. when the LSI53C875A is performing a block move for message-in phase, it does not deassert the sack/ signal for the last sreq/sack/ handshake. clear the sack/ signal using the clear sack i/o instruction. scsip[2:0] scsi phase [26:24] this 3-bit field defines the scsi information transfer phase. when the LSI53C875A operates in initiator mode, these bits are compared with the latched scsi phase bits in the scsi status one (sstat1) register. when the LSI53C875A operates in target mode, it asserts the phase defined in this field. ta b l e 5 . 2 describes the possible combinations and the corresponding scsi phase.
5-12 scsi scripts instruction set tc[23:0] transfer counter [23:0] this 24-bit field specifies the number of data bytes to be moved between the LSI53C875A and system memory. the field is stored in the dma byte counter (dbc) register. when the LSI53C875A transfers data to/from memory, the dbc register is decremented by the number of bytes transferred. in addition, the dma next address (dnad) register is incremented by the number of bytes transferred. this process is repeated until the dbc register is decremented to zero. at this time, the LSI53C875A fetches the next instruction. if bit 28 is set, indicating table indirect addressing, this field is not used. the byte count is instead fetched from a table pointed to by the data structure address (dsa) register. table 5.2 scsi information transfer phase msg c_d i_o scsi phase 00 0data-out 00 1data-in 0 1 0 command 01 1status 1 0 0 reserved 1 0 1 reserved 1 1 0 message-out 1 1 1 message-in
i/o instruction 5-13 5.3.2 second dword start address [31:0] this 32-bit field specifies the starting address of the data to move to/from memory. this field is copied to the dma next address (dnad) register. when the LSI53C875A transfers data to or from memory, the dnad register is incremented by the number of bytes transferred. when bit 29 is set, indicating indirect addressing, this address is a pointer to an address in memory that points to the data location. when bit 28 is set, indicating table indirect addressing, the value in this field is an offset into atablepointedtobythe data structure address (dsa) . the table entry contains byte count and address information. 5.4 i/o instruction i/o instructions perform the following scsi operations in target and initiator mode. these i/o operations are chosen with the opcode bits in the dma command (dcmd) register. this section describes these i/o operations. 31 0 dma scripts pointer save (dsps) register xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx opc2 opc1 opc0 target mode initiator mode 0 0 0 reselect select 0 0 1 disconnect wait disconnect 0 1 0 wait select wait reselect 011set set 1 0 0 clear clear
5-14 scsi scripts instruction set 5.4.1 first dword it[1:0] instruction type - i/o instruction [31:30] the it bit configuration (01) defines an i/o instruction ty p e . opc[2:0] opcode [29:27] the opcode bit configurations define the i/o operation performed but the opcode bit meanings change in target mode compared to initiator mode. opcode bit configurations (101, 110, and 111) are considered read/write instructions, and are described in section 5.5, ?read/write instructions.? this section describes target mode operations. target mode reselect instruction the LSI53C875A arbitrates for the scsi bus by asserting the scsi id stored in the scsi chip id (scid) register. if it loses arbitration, it tries again during the next available arbitration cycle without reporting any lost arbitration status. if the LSI53C875A wins arbitration, it attempts to reselect the scsi device whose id is defined in the destination id field of the instruction. once the LSI53C875A wins arbitration, it fetches the next instruction from the address pointed to by the dma scripts pointer (dsp) register. 31 30 29 27 26 25 24 23 20 19 16 15 11 10 9 8 7 6 5 4 3 2 0 dma command (dcmd) register dma byte counter (dbc) register it[1:0] opc[2:0] ra ti sel r endid[3:0] rcctm rack ratn r 01xxx x x x 0 0 0 0xxxx 0 0 0 0 0x x 0 0x 0 0x 0 0 0 opc2 opc1 opc0 instruction defined 000reselect 0 0 1 disconnect 010waitselect 011set 100clear
i/o instruction 5-15 this way the scripts can move on to the next instruction before the reselection completes. it continues executing scripts until a script that requires a response from the initiator is encountered. if the LSI53C875A is selected or reselected before winning arbitration, it fetches the next instruction from the address pointed to by the 32-bit jump address field stored in the dma next address (dnad) register. manually set the LSI53C875A to initiator mode if it is reselected, or to target mode if it is selected. disconnect instruction the LSI53C875A disconnects from the scsi bus by deasserting all scsi signal outputs. wait select instruction if the LSI53C875A is selected, it fetches the next instruction from the address pointed to by the dma scripts pointer (dsp) register. if reselected, the LSI53C875A fetches the next instruction from the address pointed to by the 32-bit jump address field stored in the dma next address (dnad) register. manually set the LSI53C875A to initiator mode when it is reselected. if the cpu sets the sigp bit in the interrupt status zero (istat0) register, the LSI53C875A aborts the wait select instruction and fetches the next instruction from the address pointed to by the 32-bit jump address field stored in the dma next address (dnad) register. set instruction when the sack/ or satn/ bits are set, the corresponding bits in the scsi output control latch (socl) register are set. do not set sack/ or satn/ except for testing purposes. when the target bit is set, the corresponding bit in the scsi control zero (scntl0) register is also set. when the carry bit is set, the corresponding bit in the arithmetic logic unit (alu) is set. note: none of the signals are set on the scsi bus in target mode. clear instruction
5-16 scsi scripts instruction set when the sack/ or satn/ bits are cleared, the corresponding bits are cleared in the scsi output control latch (socl) register. do not set sack/ or satn/ except for testing purposes. when the target bit is cleared, the corresponding bit in the scsi control zero (scntl0) register is cleared. when the carry bit is cleared, the corresponding bit in the alu is cleared. note: none of the signals are cleared on the scsi bus in the target mode. initiator mode select instruction the LSI53C875A arbitrates for the scsi bus by asserting the scsi id stored in the scsi chip id (scid) register. if it loses arbitration, it tries again during the next available arbitration cycle without reporting any lost arbitration status. if the LSI53C875A wins arbitration, it attempts to select the scsi device whose id is defined in the destination id field of the instruction. once the LSI53C875A wins arbitration, it fetches the next instruction from the address pointed to by the dma scripts pointer (dsp) register. this way the scripts can move to the next instruction before the selection completes. it continues executing scripts until a script that requires a response from the target is encountered. if the LSI53C875A is selected or reselected before winning arbitration, it fetches the next instruction from the address pointed to by the 32-bit jump address field stored in the dma next address (dnad) register. manually set opc2 opc1 opc0 instruction defined 0 0 0 select 0 0 1 wait disconnect 0 1 0 wait reselect 011set 100clear
i/o instruction 5-17 the LSI53C875A to initiator mode if it is reselected, or to target mode if it is selected. if the select with satn/ field is set, the satn/ signal is asserted during the selection phase. wait disconnect instruction the LSI53C875A waits for the target to perform a ?legal? disconnect from the scsi bus. a ?legal? disconnect occurs when sbsy/ and ssel/ are inactive for a minimum of one bus free delay (400 ns), after the LSI53C875A receives a disconnect message or a command complete message. wait reselect instruction if the LSI53C875A is selected before being reselected, it fetches the next instruction from the address pointed to bythe32-bitjumpaddressfieldstoredinthe dma next address (dnad) register. manually set the LSI53C875A to target mode when it is selected. if the LSI53C875A is reselected, it fetches the next instruction from the address pointed to by the dma scripts pointer (dsp) register. if the cpu sets the sigp bit in the interrupt status zero (istat0) register, the LSI53C875A aborts the wait reselect instruction and fetches the next instruction from the address pointed to by the 32-bit jump address field stored in the dma next address (dnad) register. set instruction when the sack/ or satn/ bits are set, the corresponding bits in the scsi output control latch (socl) register are set. when the target bit is set, the corresponding bit in the scsi control zero (scntl0) register is also set. when the carry bit is set, the corresponding bit in the alu is set. clear instruction when the sack/ or satn/ bits are cleared, the corresponding bits are cleared in the scsi output con- trol latch (socl) register. when the target bit is cleared, the corresponding bit in the scsi control zero (scntl0) register is cleared. when the carry bit is cleared, the corresponding bit in the alu is cleared.
5-18 scsi scripts instruction set ra relative addressing mode 26 when this bit is set, the 24-bit signed value in the dma next address (dnad) register is used as a relative displacement from the current dma scripts pointer (dsp) address. use this bit only in conjunction with the select, reselect, wait select, and wait reselect instructions. the select and reselect instructions can contain an absolute alternate jump address or a relative transfer address. ti table indirect mode 25 when this bit is set, the 24-bit signed value in the dma byte counter (dbc) register is added to the value in the data structure address (dsa) register, and used as an offset relative to the value in the data structure address (dsa) register. the scsi control three (scntl3) value, scsi id, synchronous offset and synchronous period are loaded from this address. prior to the start of an i/o, load the data structure address (dsa) withthebaseaddress of the i/o data structure. any address on a dword boundary is allowed. after a table indirect opcode is fetched, the data structure address (dsa) is added to the 24-bit signed offset value from the opcode to generate the address of the required data. both positive and negative offsets are allowed. a subsequent fetch from that address brings the data values into the chip. scripts can directly execute operating system i/o data structures, saving time at the beginning of an i/o operation. the i/o data structure can begin on any dword boundary and may cross system segment boundaries. there are two restrictions on the placement of data in system memory: ? the i/o data structure must lie within the 8 mbytes above or below the base address. ? an i/o command structure must have all four bytes contiguous in system memory, as shown below. the offset/period bits are ordered as in the scsi transfer (sxfer) register. the configuration bits are ordered as in the scsi control three (scntl3) register. config id offset/period 00
i/o instruction 5-19 use this bit only in conjunction with the select, reselect, wait select, and wait reselect instructions. use bits 25 and 26 individually or in = combination to produce the following conditions: direct uses the device id and physical address in the instruction. table indirect uses the physical jump address, but fetches data using the table indirect method. relative uses the device id in the instruction, but treats the alternate address as a relative jump. bit 25 bit 26 direct 0 0 table indirect 0 1 relative 1 0 ta bl e r e l a t i ve 1 1 command id not used not used absolute alternate address command table offset absolute alternate address command id not used not used absolute jump offset
5-20 scsi scripts instruction set table relative treats the alternate jump address as a relative jump and fetches the device id, synchronous offset, and synchronous period indirectly. the value in bits [23:0] of the first four bytes of the scripts instruction is added to the data structure base address to form the fetch address. sel select with atn/ 24 this bit specifies whether satn/ is asserted during the selection phase when the LSI53C875A is executing a select instruction. when operating in initiator mode, set this bit for the select instruction. if this bit is set on any other i/o instruction, an illegal instruction interrupt is generated. r reserved [23:20] endid[3:0] encoded scsi destination id [19:16] this 4-bit field specifies the destination scsi id for an i/o instruction. r reserved [15:11] cc set/clear carry 10 this bit is used in conjunction with a set or clear instruction to set or clear the carry bit. setting this bit withasetinstructionassertsthecarrybitinthealu. clearing this bit with a clear instruction deasserts the carry bit in the alu. tm set/clear target mode 9 this bit is used in conjunction with a set or clear instruction to set or clear target mode. setting this bit with a set instruction configures the LSI53C875A as a target device (this sets bit 0 of the scsi control zero (scntl0) register). clearing this bit with a clear instruction configures the LSI53C875A as an initiator device (this clears bit 0 of the scntl0 register). command table offset absolute jump offset
i/o instruction 5-21 r reserved [8:7] ack set/clear sack/ 6 r reserved [5:4] atn set/clear satn/ 3 these two bits are used in conjunction with a set or clear instruction to assert or deassert the corresponding scsi control signal. bit 6 controls the scsi sack/ signal. bit 3 controls the scsi satn/ signal. thesetinstructionisusedtoassertsack/and/orsatn/ on the scsi bus. the clear instruction is used to deassert sack/ and/or satn/ on the scsi bus. the corresponding bit in the scsi output control latch (socl) register is set or cleared depending on the instruction used. since sack/ and satn/ are initiator signals, they are not asserted on the scsi bus unless the LSI53C875A is operating as an initiator or the scsi loopback enable bit is set in the scsi test two (stest2) register. the set/clear scsi ack/, atn/ instruction is used after message phase block move operations to give the initiator the opportunity to assert attention before acknowledging the last message byte. for example, if the initiator wishes to reject a message, it issues an assert scsi atn instruction before a clear scsi ack instruction. r reserved [2:0] 5.4.2 second dword sa start address [31:0] this 32-bit field contains the memory address to fetch the next instruction if the selection or reselection fails. 31 0 dma scripts pointer save (dsps) register xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
5-22 scsi scripts instruction set if relative or table relative addressing is used, this value is a 24-bit signed offset relative to the current dma scripts pointer (dsp) register value. 5.5 read/write instructions the read/write instruction supports addition, subtraction, and comparison of two separate values within the chip. it performs the desired operation on the specified register and the scsi first byte received (sfbr) register, then stores the result back to the specified register or the sfbr. if the com bit dma control (dcntl bit 0) is cleared, read/write instructions cannot be used. 5.5.1 first dword it[1:0] instruction type - read/write instruction [31:30] the configuration of the it bits, the opcode bits and the operator bits define the read/write instruction type. the configuration of all these bits determine which instruction is currently selected. opc[2:0] opcode [29:27] the combinations of these bits determine if the instruction is a read/write or an i/o instruction. opcodes 0b000 through 0b100 are considered i/o instructions. o[2:0] operator [26:24] these bits are used in conjunction with the opcode bits to determine which instruction is currently selected. refer to ta bl e 5 . 1 for field definitions. d8 use data8/sfbr 23 when this bit is set, sfbr is used instead of the data8 value during a read-modify-write instruction (see ta b l e 5 . 1 ). this allows the user to add two register values. 31 30 29 27 26 24 23 22 16 15 8 7 6 0 dma command (dcmd) register dma byte counter (dbc) register it[1:0] opc[2:0] o[2:0] d8 a[6:0] immd a7 reserved - must be 0 01xxxxxxxxxxxxxxxxxxxxxxx 0 0 0 0 0 0 0
read/write instructions 5-23 a[6:0] register address - a[6:0] [22:16] it is possible to change register values from scripts in read-modify-write cycles or move to/from sfbr cycles. a[6:0] selects an 8-bit source/destination register within the LSI53C875A. immd immediate data [15:8] this 8-bit value is used as a second operand in logical and arithmetic functions. a7 upper register address line [a7] 7 this bit is used to access registers 0x80?0xff. r reserved [6:0] 5.5.2 second dword destination address [31:0] this field contains the 32-bit destination address where thedataistomove. 5.5.3 read-modify-write cycles during these cycles the register is read, the selected operation is performed, and the result is written back to the source register. the add operation is used to increment or decrement register values (or memory values if used in conjunction with a memory-to-register move operation) for use as loop counters. subtraction is not available when sfbr is used instead of data8 in the instruction syntax. to subtract one value from another when using sfbr, first xor the value to subtract (subtrahend) with 0xff, and add 1 to the resulting value. this creates the 2?s complement of the subtrahend. the two values are then added to obtain the difference. 31 0 dma scripts pointer save (dsps) register xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
5-24 scsi scripts instruction set 5.5.4 move to/from sfbr cycles all operations are read-modify-writes. however, two registers are involved, one of which is always the sfbr. ta b l e 5 . 3 shows the possible read-modify-write operations. the possible functions of this instruction are: ? write one byte (value contained within the scripts instruction) into any chip register. ? move to/from the sfbr from/to any other register. ? alter the value of a register with and, or, add, xor, shift left, or shift right operators. ? after moving values to the sfbr, the compare and jump, call, or similar instructions are used to check the value. ? a move-to-sfbr followed by a move-from-sfbr is used to perform a register-to-register move. table 5.3 read/write instructions operator opcode 111 read-modify-write opcode 110 move to sfbr opcode 101 move from sfbr 000 move data into register. syntax: ?move data8 to rega? move data into scsi first byte received (sfbr) register. syntax: ?move data8 to sfbr? move data into register. syntax: ?move data8 to rega? 001 1 shift register one bit to the leftandplacetheresultin the same register. syntax: ?move rega shl rega? shift register one bit to the left and place the result in the scsi first byte received (sfbr) register. syntax: ?move rega shl sfbr? shift the sfbr register one bit to the left and place the result in the register. syntax: ?move sfbr shl rega? 010 ordatawithregisterand place the result in the same register. syntax: ?move rega | data8 to rega? or data with register and place the result in the scsi first byte received (sfbr) register. syntax: ?move rega | data8 to sfbr? or data with sfbr and place the result in the register. syntax: ?move sfbr | data8 to rega? 011 xor data with register and place the result in the same register. syntax: ?move rega xor data8 to rega? xor data with register and place the result in the scsi first byte received (sfbr) register. syntax: ?move rega xor data8 to sfbr? xor data with sfbr and place the result in the register. syntax: ?move sfbr xor data8 to rega?
transfer control instructions 5-25 miscellaneous notes: substitute the desired register name or address for ?rega? in the syntax examples. data8 indicates eight bits of data. use sfbr instead of data8 to add two register values. 5.6 transfer control instructions this section describes the transfer control instructions. the configuration of the opcode bits define which transfer control instruction to perform. 100 and data with register and place the result in the same register. syntax: ?move rega & data8 to rega? anddatawithregisterand place the result in the scsi first byte received (sfbr) register. syntax: ?move rega & data8 to sfbr? anddatawithsfbrand place the result in the register. syntax: ?move sfbr & data8 to rega? 101 1 shift register one bit to the right and place the result in the same register. syntax: ?move rega shr rega? shift register one bit to the right and place the result in the scsi first byte received (sfbr) register. syntax: ?move rega shr sfbr? shift the sfbr register one bit to the right and place the result in the register. syntax: ?move sfbr shr rega? 110 add data to register without carry and place the result in the same register. syntax: ?move rega + data8torega? add data to register without carry and place the result in the scsi first byte received (sfbr) register. syntax: ?move rega + data8 to sfbr? adddatatosfbrwithout carry and place the result in the register. syntax: ?move sfbr + data8 to rega? 111 add data to register with carry and place the result in the same register. syntax: ?move rega + data8 to rega with carry? adddatatoregisterwith carry and place the result in the scsi first byte received (sfbr) register. syntax: ?move rega + data8 to sfbr with carry? adddatatosfbrwithcarry andplacetheresultinthe register. syntax: ?move sfbr + data8 to rega with carry? 1. data is shifted through the carry bit and the carry bit is shifted into the data byte. table 5.3 read/write instructions (cont.) operator opcode 111 read-modify-write opcode 110 move to sfbr opcode 101 move from sfbr
5-26 scsi scripts instruction set 5.6.1 first dword it[1:0] instruction type - transfer control instruction [31:30] the it bit configuration (10) defines the transfer control instruction type. opc[2:0] opcode [29:27] this 3-bit field specifies the type of transfer control instruction to execute. all transfer control instructions can be conditional. they can be dependent on a true/false comparison of the alu carry bit or a comparison of the scsi information transfer phase with the phase field, and/or a comparison of the first byte received with the data compare field. each instruction can operate in initiator or target mode. transfer control instructions are shown in ta b l e 5 . 4 . jump instruction the LSI53C875A can do a true/false comparison of the alu carry bit, or compare the phase and/or data as defined by the phase compare, data compare and true/false bit fields. if the comparisons are true, then it loads the dma scripts pointer (dsp) register with the contents of the 31 30 29 27 26 24 23 22 21 20 19 18 17 16 15 8 7 0 dma command (dcmd) register dma byte counter (dbc) register it[1:0] opc[2:0] scsip[2:0] ra r ct if jmp cd cp wvp dcm-data compare mask dcv-data compare value 10xxx x x x x 0 x x x x x x xxxxxxxxxxxxxxxx table 5.4 transfer control instructions opc2 opc1 opc0 instruction defined 000jump 001call 010return 0 1 1 interrupt 1 x x reserved
transfer control instructions 5-27 dma scripts pointer save (dsps) register. the dsp register now contains the address of the next instruction. if the comparisons are false, the LSI53C875A fetches the next instruction from the address pointed to by the dma scripts pointer (dsp) register, leaving the instruction pointer unchanged. call instruction the LSI53C875A can do a true/false comparison of the alu carry bit, or compare the phase and/or data as defined by the phase compare, data compare, and true/false bit fields. if the comparisons are true, it loads the dma scripts pointer (dsp) register with the contents of the dma scripts pointer save (dsps) register and that address value becomes the address of the next instruction. when the LSI53C875A executes a call instruction, the instruction pointer contained in the dsp register is stored in the te m p o r a r y ( t e m p ) register. since the temp register is not a stack and can only hold one dword, nested call instructions are not allowed. if the comparisons are false, the LSI53C875A fetches the next instruction from the address pointed to by the dsp register and the instruction pointer is not modified. return instruction the LSI53C875A can do a true/false comparison of the alu carry bit, or compare the phase and/or data as defined by the phase compare, data compare, and true/false bit fields. if the comparisons are true, it loads the dma scripts pointer (dsp) register with the contents of the dma scripts pointer save (dsps) register. that address value becomes the address of the next instruction. when a return instruction is executed, the value stored in the temporary (temp) register is returned to the dsp register. the LSI53C875A does not check to see whether the call instruction has already been executed. it does not generate an interrupt if a return instruction is executed without previously executing a call instruction.
5-28 scsi scripts instruction set if the comparisons are false, the LSI53C875A fetches the next instruction from the address pointed to by the dsp register and the instruction pointer is not modified. interrupt instruction the LSI53C875A can do a true/false comparison of the alu carry bit, or compare the phase and/or data as defined by the phase compare, data compare, and true/false bit fields. if the comparisons are true, the LSI53C875A generates an interrupt by asserting the irq/ signal. the 32-bit address field stored in the dma scripts pointer save (dsps) register can contain a unique interrupt service vector. when servicing the interrupt, this unique status code allows the interrupt service routine to quickly identify the point at which the interrupt occurred. the LSI53C875A halts and the dma scripts pointer (dsp) register must be written to before starting any further operation. interrupt-on-the-fly instruction the LSI53C875A can do a true/false comparison of the alu carry bit or compare the phase and/or data as defined by the phase compare, data compare, and true/false bit fields. if the comparisons are true, and the interrupt-on-the-fly bit ( interrupt status one (istat1) bit 2) is set, the LSI53C875A asserts the interrupt-on-the- fly bit. scsip[2:0] scsi phase [26:24] this 3-bit field corresponds to the three scsi bus phase signals that are compared with the phase lines latched when sreq/ is asserted. comparisons can be performed to determine the scsi phase actually being driven on the scsi bus. ta b l e 5 . 5 describes the possible combinations and their corresponding scsi phase. these bits are only valid when the LSI53C875A is operating in initiator mode. clear these bits when the LSI53C875A is operating in target mode.
transfer control instructions 5-29 ra relative addressing mode 23 when this bit is set, the 24-bit signed value in the dma scripts pointer save (dsps) register is used as a relative offset from the current dma scripts pointer (dsp) address (which is pointing to the next instruction, not the one currently executing). the relative mode does not apply to return and interrupt scripts. jump/call an absolute address start execution at the new absolute address. jump/call a relative address start execution at the current address plus (or minus) the relative offset. the scripts program counter is a 32-bit value pointing to the scripts currently under execution by the LSI53C875A. the next address is formed by adding the 32-bit program counter to the 24-bit signed value of the last 24 bits of the jump or call instruction. because it is table 5.5 scsi phase comparisons msg c/d i/o scsi phase 000data-out 001data-in 0 1 0 command 0 1 1 status 1 0 0 reserved 1 0 1 reserved 1 1 0 message-out 1 1 1 message-in command condition codes absolute alternate address command condition codes don?t care alternate jump offset
5-30 scsi scripts instruction set signed (2?s complement), the jump can be forward or backward. a relative transfer can be to any address within a 16 mbyte segment. the program counter is combined with the 24-bit signed offset (using addition or subtraction) to form the new execution address. scripts programs may contain a mixture of direct jumps and relative jumps to provide maximum versatility when writing scripts. for example, major sections of code can be accessed with far calls using the 32-bit physical address, then local labels can be called using relative transfers. if a script is written using only relative transfers it does not require any run time alteration of physical addresses, and can be stored in and executed from a prom. r reserved 22 ct carry test 21 when this bit is set, decisions based on the alu carry bit can be made. true/false comparisons are legal, but data compare and phase compare are illegal. if interrupt-on-the-fly 20 when this bit is set, the interrupt instruction does not halt the scripts processor. once the interrupt occurs, the interrupt-on-the-fly bit ( interrupt status one (istat1) bit 2) is asserted. jmp jump if true/false 19 this bit determines whether the LSI53C875A branches when a comparison is true or when a comparison is false. this bit applies to phase compares, data compares, and carry tests. if both the phase compare and data compare bits are set, then both compares must be true to branch on a true condition. both compares must be falsetobranchonafalsecondition.
transfer control instructions 5-31 cd compare data 18 when this bit is set, the first byte received from the scsi data bus (contained in the scsi first byte received (sfbr) register) is compared with the data to be compared field in the transfer control instruction. the wait for valid phase bit controls when this compare occurs. the jump if true/false bit determines the condition (true or false) to branch on. cp compare phase 17 when the LSI53C875A is in initiator mode, this bit controls phase compare operations. when this bit is set, the scsi phase signals (latched by sreq/) are compared to the phase field in the transfer control instruction. if they match, the comparison is true. the wait for valid phase bit controls when the compare occurs. when the LSI53C875A is operating in target mode and this bit is set it tests for an active scsi satn/ signal. wvp wait for valid phase 16 if the wait for valid phase bit is set, the LSI53C875A waits for a previously unserviced phase before comparing the scsi phase and data. if the wait for valid phase bit is cleared, the LSI53C875A compares the scsi phase and data immediately. dcm data compare mask [15:8] the data compare mask allows a script to test certain bits within a data byte. during the data compare, if any mask bits are set, the corresponding bit in the scsi first byte received (sfbr) data byte is ignored. for instance, a mask of 0b01111111 and data compare value of 0b1xxxxxxx allows the scripts processor to determine whether or not the high order bit is set while ignoring the remaining bits. bit 19 result of compare action 0 false jump taken 0truenojump 1falsenojump 1 true jump taken
5-32 scsi scripts instruction set dcv data compare value [7:0] this 8-bit field is the data compared against the register. these bits are used in conjunction with the data compare mask field to test for a particular data value. 5.6.2 second dword jump address [31:0] this 32-bit field contains the address of the next instruction to fetch when a jump is taken. once the LSI53C875A fetches the instruction from the address pointed to by these 32 bits, this address is incremented by 4, loaded into the dma scripts pointer (dsp) register and becomes the current instruction pointer. 5.7 memory move instructions for memory move instructions, bits 5 and 4 (siom and diom) in the dma mode (dmode) register determine whether the source or destination addresses reside in memory or i/o space. by setting these bits appropriately, data may be moved within memory space, within i/o space, or between the two address spaces. the memory move instruction is used to copy the specified number of bytes from the source address to the destination address. allowing the LSI53C875A to perform memory moves frees the system processor for other tasks and moves data at higher speeds than available from current dma controllers. up to 16 mbytes may be transferred with one instruction. there are two restrictions: ? both the source and destination addresses must start with the same address alignment a[1:0]. if the source and destination are not aligned, then an illegal instruction interrupt occurs. for the pci cache line size register setting to take effect, the source and destination must be the same distance from a cache line boundary. 31 0 dma scripts pointer save (dsps) register xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
memory move instructions 5-33 ? indirect addresses are not allowed. a burst of data is fetched from the source address, put into the dma fifo and then written out to the destination address. the move continues until the byte count decrements to zero, then another scripts is fetched from system memory. the dma scripts pointer save (dsps) and data structure address (dsa) registers are additional holding registers used during the memory move. however, the contents of the data structure address (dsa) register are preserved. 5.7.1 first dword it[2:0] instruction type - memory move [31:29] the it bit configuration (110) defines a memory move instruction type. r reserved [28:25] these bits are reserved and must be zero. if any of these bits are set, an illegal instruction interrupt occurs. nf no flush 24 when this bit is set, the LSI53C875A performs a memory move without flushing the prefetch unit. when this bit is cleared, the memory move instruction automatically flushes the prefetch unit. use the no flush option if the source and destination are not within four instructions of the current memory move instruction. note: this bit has no effect unless the prefetch enable bit in the dma control (dcntl) register is set. for information on scripts instruction prefetching, see chapter 2 . tc[23:0] transfer counter [23:0] the number of bytes to transfer is stored in the lower 24 bits of the first instruction word. 31 29 28 25 24 23 0 dma command (dcmd) register dma byte counter (dbc) register it[2:0] r nf transfer counter (tc) [23:0] 110 0 0 0 0 x xxxxxxxxxxxxxxxxxxxxxxxx
5-34 scsi scripts instruction set 5.7.2 read/write system memory from scripts by using the memory move instruction, single or multiple register values are transferred to or from system memory. because the LSI53C875A responds to addresses as defined in the base address register zero (i/o) or base address register one (memory) registers, it can be accessed during a memory move operation if the source or destination address decodes to within the chip?s register space. if this occurs, the register indicated by the lower seven bits of the address is taken as the data source or destination. in this way, register values are saved to system memory and later restored, and scripts can make decisions based on data values in system memory. the sfbr is not writable using the cpu, and therefore not by a memory move. however, it can be loaded using scripts read/write operations. toloadthesfbrwithabytestoredinsystemmemory,firstmovethe byte to an intermediate LSI53C875A register (for example, a scratch register), and then to the sfbr. the same address alignment restrictions apply to register access operations as to normal memory-to-memory transfers. 5.7.3 second dword - dsps register [31:0] these bits contain the source address of the memory move. 31 0 dma scripts pointer save (dsps) register xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
load and store instructions 5-35 5.7.4 third dword temp register [31:0] these bits contain the destination address for the memory move. 5.8 load and store instructions the load and store instructions provide a more efficient way to move data from/to memory to/from an internal register in the chip without using the normal memory move instruction. the load and store instructions are represented by two dword opcodes. the first dword contains the dma command (dcmd) and dma byte counter (dbc) register values. the second dword contains the dma scripts pointer save (dsps) value. this is either the actual memory location of where to load and store, or the offset from the data structure address (dsa) , depending on the value of bit 28 (dsa relative). a maximum of 4 bytes may be moved with these instructions. the register address and memory address must have the same byte alignment, and the count set such that it does not cross dword boundaries. the memory address may not map back to the chip, excluding ram and rom. if it does, a pci read/write cycle occurs (the data does not actually transfer to/from the chip), and the chip issues an interrupt (illegal instruction detected) immediately following. 31 0 temporary (temp) register xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx bit a1 bit a0 number of bytes allowed to load and store 0 0 one, two, three or four 0 1 one, two, or three 10oneortwo 11one
5-36 scsi scripts instruction set the siom and diom bits in the dma mode (dmode) register determine whether the destination or source address of the instruction is in memory space or i/o space, as illustrated in the following table. the load and store utilizes the pci commands for i/o read and i/o write to access the i/o space. 5.8.1 first dword it[2:0] instruction type [31:29] these bits should be 0b111, indicating the load and store instruction. dsa dsa relative 28 when this bit is cleared, the value in the dma scripts pointer save (dsps) is the actual 32-bit memory address used to perform the load and store to/from. when this bit is set, the chip determines the memory address to perform the load and store to/from by adding the 24-bit signed offset value in the dma scripts pointer save (dsps) to the data structure address (dsa) . r reserved [27:26] nf no flush (store instruction only) 25 when this bit is set, the LSI53C875A performs a store without flushing the prefetch unit. when this bit is cleared, the store instruction automatically flushes the prefetch unit. use no flush if the source and destination are not within four instructions of the current store instruction. this bit has no effect on the load instruction. bit source destination siom (load) memory register diom (store) register memory 31 29 28 27 26 25 24 23 22 16 15 3 2 0 dma command (dcmd) register dma byte counter (dbc) register it[2:0] dsa rnfls r ra[6:0] rbc 111 x 0 0xx 0xxxxxxx 0 0 0 0 0 0 0 0 0 0 0 0 0xxx
load and store instructions 5-37 note: this bit has no effect unless the prefetch enable bit in the dma control (dcntl) register is set. ls load and store 24 when this bit is set, the instruction is a load. when cleared, it is a store. r reserved 23 ra[6:0] register address [22:16] a[6:0] selects the register to load and store to/from within the LSI53C875A. r reserved [15:3] bc byte count [2:0] this value is the number of bytes to load and store. 5.8.2 second dword memory i/o address / dsa offset [31:0] this is the actual memory location of where to load and store, or the offset from the data structure address (dsa) register value. 31 0 dma scripts pointer save (dsps) register - memory i/o address/dsa offset xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
5-38 scsi scripts instruction set
LSI53C875A pci to ultra scsi controller 6-1 chapter 6 electrical specifications this section specifies the LSI53C875A electrical and mechanical characteristics. it is divided into the following sections: ? section 6.1, ?dc characteristics? ? section 6.2, ?tolerant technology electrical characteristics? ? section 6.3, ?ac characteristics? ? section 6.4, ?pci and external memory interface timing diagrams? ? section 6.5, ?scsi timing diagrams? ? section 6.6, ?package diagrams? 6.1 dc characteristics this section of the manual describes the LSI53C875A dc characteristics. ta bl e 6 . 1 through ta bl e 6 . 1 0 give current and voltage specifications.
6-2 electrical specifications table 6.1 absolute maximum stress ratings 1 1. stresses beyond those listed above may cause permanent damage to the device. these are stress ratings only; functional operation of the device at these or any other conditions beyond those indicatedinthe operating conditions section of the manual is not implied. symbol parameter min max unit test conditions t stg storage temperature ? 55 150 c? v dd supply voltage ? 0.5 4.5 v ? v in input voltage v ss ? 0.3 5.55 v scsi 5 v tolerant pads i lp 2 2. ? 2v dc characteristics 6-3 table 6.4 bidirectional signals?mad[7:0], mas/[1:0], mce/, moe/, mwe/ symbol parameter min max unit test conditions v ih input high voltage 2.0 5.25 v ? v il input low voltage v ss ? 0.5 0.8 v ? v oh output high voltage 2.4 v dd v ? 4ma v ol output low voltage v ss 0.4 v 4 ma i oz 3-state leakage ? 10 10 a? i pull pull-down current 12.5 +50 a? table 6.5 bidirectional signals?gpio0_fetch/, gpio1_master/, gpio[2:4] symbol parameter min max unit test conditions v ih input high voltage 2.0 5.25 v ? v il input low voltage v ss ? 0.5 0.8 v ? v oh output high voltage 2.4 v dd v ? 8ma v ol output low voltage v ss 0.4 v 8 ma i oz 3-state leakage ? 10 10 a? i pull pull-down current 12.5 +50 a?
6-4 electrical specifications table 6.6 bidirectional signals?ad[31:0], c_be[3:0]/, frame/, irdy/, trdy/, devsel/,stop/,perr/,par symbol parameter min max unit test conditions v ih input high voltage 0.5 v dd 5.25 v ? v il input low voltage v ss 0.3 v dd v? v oh output high voltage 0.9 v dd v dd v ? 16 ma v ol output low voltage v ss 0.1 v dd v16ma i oz 3-state leakage ? 10 10 a? i pull pull-down current 25 ? a? table 6.7 input signals?clk, gnt/, idsel, rst/, sclk, tck, tdi, test_hsc, test_rst, tms, trst/ symbol parameter min max unit test conditions v ih input high voltage 0.5 v dd 5.25 v ? v il input low voltage v ss 0.3 v dd v? i in input leakage ? 10 10 a? i pull pull-up current - only on tck, tdi, test_hsc, test_rst, tms, trst/ ? 50 ? 12.5 a? table 6.8 output signal?tdo symbol parameter min max unit test conditions v oh output high voltage 2.4 v dd v ? 4ma v ol output low voltage v ss 0.4 v 4 ma i oz 3-state leakage ? 10 10 a?
tolerant technology electrical characteristics 6-5 6.2 tolerant technology electrical characteristics the LSI53C875A features tolerant technology, which includes active negation on the scsi drivers and input signal filtering on the scsi receivers. active negation actively drives the scsi request, acknowledge, data, and parity signals high rather than allowing them to be passively pulled up by terminators. ta b l e 6 . 1 1 provides electrical characteristics for se scsi signals. figure 6.1 through figure 6.5 provide reference information for testing scsi signals. table 6.9 output signals?irq/, mac/_testout, req/ symbol parameter min max unit test conditions v oh output high voltage 0.9 v dd v dd v ? 16 ma v ol output low voltage v ss 0.1 v dd v16ma i oz 3-state leakage ? 10 10 a? i pull pull-down current - only on irq/ ? 50 ? 12.5 a? table 6.10 output signal?serr/ symbol parameter min max unit test conditions v ol output low voltage v ss 0.1 v dd v16ma i oz 3-state leakage ? 10 10 a?
6-6 electrical specifications table 6.11 tolerant technology electrical characteristics for se scsi signals symbol parameter min 1 1. these values are guaranteed by periodic characterization; they are not 100% tested on every device. max unit test conditions v oh 2 2. active negation outputs only: data, parity, sreq/, sack/. output high voltage 2.0 v dd +0.3 v i oh =7ma v ol output low voltage v ss 0.5 v i ol =48ma v ih input high voltage 2.0 v dd +0.3 v ? v il input low voltage v ss ? 0.3 0.8 v referenced to v ss v ik input clamp voltage ? 0.66 ? 0.77 v v dd =4.75;i i = ? 20 ma v th threshold, high to low 1.0 1.2 v ? v tl threshold, low to high 1.4 1.6 v ? v th ?v tl hysteresis 300 500 mv ? i oh 2 output high current 2.5 24 ma v oh =2.5v i ol output low current 100 200 ma v ol =0.5v i osh 2 short-circuit output high current ? 625 ma output driving low, pin shorted to v dd supply 3 3. single pin only; irreversible damage may occur if sustained for one second. i osl short-circuit output low current ? 95 ma output driving high, pin shorted to v ss supply i lh input high leakage ? 20 a ? 0.5 < v dd <5.25 v pin =2.7v i ll input low leakage ? ? 20 a ? 0.5 < v dd <5.25 v pin =0.5v r i input resistance 20 ? m ? scsi pins c p capacitance per pin ? 15 pf pqfp t r 2 rise time, 10% to 90% 4.0 18.5 ns figure 6.1 t f fall time, 90% to 10% 4.0 18.5 ns figure 6.1 dv h /dt slew rate, low to high 0.15 0.50 v/ns figure 6.1 dv l /dt slew rate, high to low 0.15 0.50 v/ns figure 6.1 esd electrostatic discharge 2 ? kv mil-std-883c; 3015-7 latch-up 100 ? ma ? filter delay 20 30 ns figure 6.2 ultra filter delay 10 15 ns figure 6.2 extended filter delay 40 60 ns figure 6.2
tolerant technology electrical characteristics 6-7 figure 6.1 rise and fall time test condition figure 6.2 scsi input filtering figure 6.3 hysteresis of scsi receivers + ? 2.5 v 47 ? 20 pf req/ or sack/ input t 1 v th note: t 1 is the input filtering period. 1 0 received logic level input voltage (volts) 1.1 1.3 1.5 1.7
6-8 electrical specifications figure 6.4 input current as a function of input voltage figure 6.5 output current as a function of output voltage +40 +20 0 ? 20 ? 40 ? 4 0 4 8 12 16 ? 0.7 v 8.2 v high-z output active input voltage (volts) input current (milliamperes) 14.4 v output sink current (milliamperes) 0 ? 200 ? 400 ? 600 ? 800 012345 output voltage (volts) output source current (milliamperes) output voltage (volts) 0123 45 100 80 60 40 20 0
ac characteristics 6-9 6.3 ac characteristics the ac characteristics described in this section apply over the entire range of operating conditions (refer to the dc characteristics section). chip timings are based on simulation at worst case voltage, temperature, and processing. timing was developed with a load capacitance of 50 pf. ta b l e 6 . 1 2 and figure 6.6 provide external clock timing data. figure 6.6 external clock table 6.12 external clock 1 1. timings are for an external 40 mhz clock. symbol parameter min max unit t 1 bus clock cycle time 30 dc ns scsi clock cycle time (sclk) 2 2. this parameter must be met to ensure scsi timings are within specification. 25 60 ns t 2 clk low time 3 3. duty cycle not to exceed 60/40. 10 ? ns sclk low time 3 633ns t 3 clk high time 3 12 ? ns sclk high time 3 10 33 ns t 4 clk slew rate 1 ? v/ns sclk slew rate 1 ? v/ns clk, sclk 1.4 v t 1 t 3 t 4 t 2
6-10 electrical specifications ta b l e 6 . 1 3 and figure 6.7 provide reset input timing data. figure 6.7 reset input ta b l e 6 . 1 4 and figure 6.8 provide interrupt output timing data. table 6.13 reset input symbol parameter min max unit t 1 reset pulse width 10 ? t clk t 2 reset deasserted setup to clk high 0 ? ns t 3 mad setup time to clk high (for configuring the mad bus only) 20 ? ns t 4 mad hold time from clk high (for configuring the mad bus only) 20 ? ns t 2 note: 1. when enabled. clk rst/ mad 1 valid data t 3 t 4 t 1 table 6.14 interrupt output symbol parameter min max unit t 1 clk high to irq/ low 2 11 ns t 2 clk high to irq/ high 2 11 ns t 3 irq/ deassertion time 3 ? clk
pci and external memory interface timing diagrams 6-11 figure 6.8 interrupt output 6.4 pci and external memory interface timing diagrams figure 6.9 through figure 6.32 represent signal activity when the LSI53C875A accesses the pci bus. this section includes timing diagrams for access to three groups of memory configurations. the first group applies to target timing . the second group applies to initiator timing . the third group applies to external memory timing . note: multiple byte accesses to the external memory bus increase the read or write cycle by 11 clocks for each additional byte. timing diagrams included in this section are: ? target timing ? pci configuration register read ? pci configuration register write ? 32-bit operating register/scripts ram read ? 64-bit address operating register/scripts ram read ? 32-bit operating register/scripts ram write ? 64-bit address operating register/scripts ram write ? initiator timing ? nonburst opcode fetch, 32-bit address and data ? burst opcode fetch, 32-bit address and data ? back-to-back read, 32-bit address and data ? back-to-back write, 32-bit address and data clk irq/ t 3 t 1 t 2
6-12 electrical specifications ? burst read, 32-bit address and data ? burst read, 64-bit address and data ? burst write, 32-bit address and data ? burst write, 64-bit address and 32-bit data ? external memory timing ? external memory read ? external memory write ? normal/fast memory ( 128 kbytes) single byte access read cycle ? normal/fast memory ( 128 kbytes) single byte access write cycle ? nornal/fast memory ( 128 kbytes) multiple byte access read cycle ? normal/fast memory ( 128 kbytes) multiple byte access write cycle ?slowmemory( 128 kbytes) read cycle ?slowmemory( 128 kbytes) write cycle ? 64 kbytes rom read cycle ? 64 kbyte rom write cycle
pci and external memory interface timing diagrams 6-13 6.4.1 target timing the tables and figures in this section describe target timings. figure 6.9 pci configuration register read table 6.15 pci configuration register read symbol parameter min max unit t 1 shared signal input setup time 7 ? ns t 2 shared signal input hold time 0 ? ns t 3 clk to shared signal output valid ? 11 ns clk frame/ ad (driven by master-addr; LSI53C875A-data) c_be/ (driven by master ) pa r (driven by master-addr; LSI53C875A-data) irdy/ (driven by master) trdy/ (driven by LSI53C875A) stop/ (driven by LSI53C875A) devsel/ (driven by LSI53C875A) idsel (driven by master) t 1 t 2 data out byte enable t 1 t 1 t 1 t 2 t 1 t 2 t 2 t 2 t 1 t 2 t 2 t3 t 3 t 3 t 3 out in addr in (driven by system) (driven by system) cmd
6-14 electrical specifications figure 6.10 pci configuration register write table 6.16 pci configuration register write symbol parameter min max unit t 1 shared signal input setup time 7 ? ns t 2 shared signal input hold time 0 ? ns t 3 clk to shared signal output valid ? 11 ns clk (driven by system) frame/ (driven by master) ad (driven by master) c_be/ (driven by master) pa r (driven by master) irdy/ (driven by master) trdy/ (driven by LSI53C875A) stop/ (driven by LSI53C875A) devsel/ (driven by LSI53C875A) idsel (driven by master) t 1 t 2 t 3 data in byte enable addr in cmd t 1 t 2 t 2 t 2 t 2 t 3 t 1 t 1 t 1 t 2 t 2 t 1 t 2 t 1
pci and external memory interface timing diagrams 6-15 figure 6.11 32-bit operating register/scripts ram read table 6.17 32-bit operating register/scripts ram read symbol parameter min max unit t 1 shared signal input setup time 7 ? ns t 2 shared signal input hold time 0 ? ns t 3 clk to shared signal output valid ? 11 ns clk (driven by system) frame/ (driven by master) ad (driven by master-addr; LSI53C875A-data) c_be/ (driven by master) pa r (driven by master-addr; LSI53C875A-data) irdy/ (driven by master) trdy/ (driven by LSI53C875A) stop/ (driven by LSI53C875A) devsel/ (driven by LSI53C875A) cmd byte enable data out out in t 1 t 2 t 3 addr in t 1 t 1 t 1 t 2 t 2 t 2 t 3 t 3 t 3 t 2 t 2
6-16 electrical specifications figure 6.12 64-bit address operating register/scripts ram read table 6.18 64-bit address operating register/scripts ram read symbol parameter min max unit t 1 shared signal input setup time 7 ? ns t 2 shared signal input hold time 0 ? ns t 3 clk to shared signal output valid ? 11 ns clk (driven by system) frame/ (driven by master) ad[31:0] (driven by master-addr; LSI53C875A-data) c_be[3:0] (driven by master) pa r (driven by master-addr; LSI53C875A-data) irdy/ (driven by master) trdy/ (driven by LSI53C875A) stop/ (driven by LSI53C875A) devsel/ (driven by LSI53C875A) t 1 t 2 t 3 out in byte enable bus dual addr addr lo addr hi data out t 1 t 1 t 1 t 2 t 2 t 2 t 2 t 1 t 1 t 3 t 3 t 3 t 3 in cmd
pci and external memory interface timing diagrams 6-17 figure 6.13 32-bit operating register/scripts ram write table 6.19 32-bit operating register/scripts ram write symbol parameter min max unit t 1 shared signal input setup time 7 ? ns t 2 shared signal input hold time 0 ? ns t 3 clk to shared signal output valid ? 11 ns clk (driven by system) frame/ (driven by master) ad (driven by master) c_be/ (driven by master) pa r (driven by master) irdy/ (driven by master) trdy/ (driven by LSI53C875A) stop/ (driven by LSI53C875A) devsel/ (driven by LSI53C875A) addr in cmd in t 3 in t 1 t 1 t 1 t 1 t 1 t 1 t 2 t 2 t 2 t 2 t 2 t 2 t 1 t 3 t 2 t 2
6-18 electrical specifications figure 6.14 64-bit address operating register/scripts ram write table 6.20 64-bit address operating register/scripts ram write symbol parameter min max unit t 1 shared signal input setup time 7 ? ns t 2 shared signal input hold time 0 ? ns t 3 clk to shared signal output valid ? 11 ns bus addr lo addr hi data in in t 2 t 3 clk (driven by system) frame/ (driven by master) ad (driven by master) c_be/ (driven by master) pa r (driven by master) irdy/ (driven by master) trdy/ (driven by LSI53C875A) stop/ (driven by LSI53C875A) devsel/ (driven by LSI53C875A) cmd byte enable in in dual addr t 1 t 1 t 1 t 1 t 1 t 1 t 1 t 1 t 2 t 2 t 2 t 2 t 2 t 3 t 2 t 2 t 2
pci and external memory interface timing diagrams 6-19 6.4.2 initiator timing the tables and figures in this section describe LSI53C875A initiator timings. table 6.21 nonburst opcode fetch, 32-bit address and data symbol parameter min max unit t 1 shared signal input setup time 7 ? ns t 2 shared signal input hold time 0 ? ns t 3 clk to shared signal output valid 2 11 ns t 4 side signal input setup time 10 ? ns t 5 side signal input hold time 0 ? ns t 6 clk to side signal output valid 2 12 ns t 7 clk high to gpio0_fetch/ low ? 20 ns t 8 clk high to gpio0_fetch/ high ? 20 ns t 9 clk high to gpio1_master/ low ? 20 ns t 10 clk high to gpio1_master/ high ? 20 ns
6-20 electrical specifications figure 6.15 nonburst opcode fetch, 32-bit address and data clk (driven by system) frame/ (driven by LSI53C875A) ad (driven by LSI53C875A- c_be/ (driven by LSI53C875A) pa r (driven by LSI53C875A- irdy/ (driven by LSI53C875A) trdy/ (driven by target) stop/ (driven by target) devsel/ (driven by target) addr/ target-data) addr; target-data) gnt/ (driven by arbiter) req/ (driven by LSI53C875A) gpio1_master/ (driven by LSI53C875A) gpio0_fetch/ (driven by LSI53C875A) addr out addr out cmd be be cmd t 1 t 2 t 3 data in t 10 t 8 t 7 t 9 t 4 t 6 t 5 t 1 t 1 t 1 t 2 t 2 t 2 t 3 t 3 t 3 t 3 t 3 data in
pci and external memory interface timing diagrams 6-21 table 6.22 burst opcode fetch, 32-bit address and data symbol parameter min max unit t 1 shared signal input setup time 7 ? ns t 2 shared signal input hold time 0 ? ns t 3 clk to shared signal output valid 2 11 ns t 4 side signal input setup time 10 ? ns t 5 side signal input hold time 0 ? ns t 6 clk to side signal output valid 2 12 ns t 7 clk high to gpio0_fetch/ low ? 20 ns t 8 clk high to gpio0_fetch/ high ? 20 ns t 9 clk high to gpio1_master/ low ? 20 ns t 10 clk high to gpio1_master/ high ? 20 ns
6-22 electrical specifications figure 6.16 burst opcode fetch, 32-bit address and data clk (driven by system) frame/ (driven by LSI53C875A) ad (driven by LSI53C875A- c_be/ (driven by LSI53C875A) pa r (driven by LSI53C875A- irdy/ (driven by LSI53C875A) trdy/ (driven by target) stop/ (driven by target) devsel/ (driven by target) addr/ target-data) addr; target-data) gnt/ (driven by arbiter) req/ (driven by LSI53C875A) gpio1_master/ (driven by LSI53C875A) gpio0_fetch/ (driven by LSI53C875A) t 7 t 8 t 9 t 10 t 6 t 5 t 4 t 3 t 2 t 1 in be cmd addr out out in t 3 t 3 t 3 t 3 t 3 t 3 t 2 t 2 t 2 t 1 t 1 t 1 data in data in
pci and external memory interface timing diagrams 6-23 table 6.23 back-to-back read, 32-bit address and data symbol parameter min max unit t 1 shared signal input setup time 7 ? ns t 2 shared signal input hold time 0 ? ns t 3 clk to shared signal output valid 2 11 ns t 4 side signal input setup time 10 ? ns t 5 side signal input hold time 0 ? ns t 6 clk to side signal output valid 2 12 ns t 9 clk high to gpio1_master/ low ? 20 ns t 10 clk high to gpio1_master/ high ? 20 ns
6-24 electrical specifications figure 6.17 back-to-back read, 32-bit address and data clk (driven by system) frame/ (driven by LSI53C875A) ad (driven by LSI53C875A- c_be/ (driven by LSI53C875A) pa r (driven by LSI53C875A- irdy/ (driven by LSI53C875A) trdy/ (driven by target) stop/ (driven by target) devsel/ (driven by target) addr; target-data ) addr; target-data) gnt/ (driven by arbiter) req/ (driven by LSI53C875A) gpio1_master/ (driven by LSI53C875A) gpio0_fetch/ (driven by LSI53C875A ) out cmd be addr out t 9 data in in out be cmd addr out t 6 t 5 t 3 t 4 t 3 t 3 t 3 t 3 t 1 t 2 t 2 t 1 t 2 t 1 t 2 t 10 t 1 data in in
pci and external memory interface timing diagrams 6-25 table 6.24 back-to-back write, 32-bit address and data symbol parameter min max unit t 1 shared signal input setup time 7 ? ns t 2 shared signal input hold time 0 ? ns t 3 clk to shared signal output valid 2 11 ns t 4 side signal input setup time 10 ? ns t 5 side signal input hold time 0 ? ns t 6 clk to side signal output valid 2 12 ns t 9 clk high to gpio1_master/ low ? 20 ns t 10 clk high to gpio1_master/ high ? 20 ns
6-26 electrical specifications figure 6.18 back-to-back write, 32-bit address and data clk (driven by system) frame/ (driven by LSI53C875A) ad (driven by LSI53C875A- c_be/ (driven by LSI53C875A) pa r (driven by LSI53C875A- irdy/ (driven by LSI53C875A) trdy/ (driven by target) stop/ (driven by target) devsel/ (driven by target) addr; target-data) addr; target-data) gnt/ (driven by arbiter) req/ (driven by LSI53C875A) gpio1_master/ (driven by LSI53C875A) gpio0_fetch/ (driven by LSI53C875A) t 3 t 2 t 4 t 1 t 5 t 6 t 9 t 10 addr out data out cmd be addr out data out cmd be t 3 t 3 t 3 t 3 t 3 t 3 t 1 t 2 t 3
pci and external memory interface timing diagrams 6-27 table 6.25 burst read, 32-bit address and data symbol parameter min max unit t 1 shared signal input setup time 7 ? ns t 2 shared signal input hold time 0 ? ns t 3 clk to shared signal output valid 2 11 ns
6-28 electrical specifications figure 6.19 burst read, 32-bit address and data t 1 t 2 clk gpio0_fetch/ (driven by LSI53C875A) gpio1_master/ (driven by LSI53C875A) req/ (driven by LSI53C875A) pa r (driven by LSI53C875A- irdy/ (driven by LSI53C875A) trdy/ (driven by target) stop/ (driven by target) devsel/ (driven by target) ad (driven by LSI53C875A- c_be/ (driven by LSI53C875A) t 3 cmd gnt/ (driven by arbiter) frame/ (driven by LSI53C875A) addr out t 2 addr; target-data) addr; target-data) be data in out in in
pci and external memory interface timing diagrams 6-29 table 6.26 burst read, 64-bit address and data symbol parameter min max unit t 1 shared signal input setup time 7 ? ns t 2 shared signal input hold time 0 ? ns t 3 clk to shared signal output valid 2 11 ns t 10 clk high to gpio1_master/high ? 20 ns
6-30 electrical specifications figure 6.20 burst read, 64-bit address and data t 1 t 2 clk gpio0_fetch/ (driven by LSI53C875A) gpio1_master/ (driven by LSI53C875A) req/ (driven by LSI53C875A) pa r (addr drvn by LSI53C875A; irdy/ (driven by LSI53C875A) trdy/ (driven by target) stop/ (driven by target) devsel/ (driven by target) ad[31:0] (addr driven by LSI53C875A- c_be[3:0]/ (driven by LSI53C875A) t 3 gnt/ (driven by arbiter) frame/ (driven by LSI53C875A) addr out lo t 2 data driven by target) data drvn by target) be t 1 data in in out in in t 10 bus dual addr cmd t 2 addr out hi
pci and external memory interface timing diagrams 6-31 table 6.27 burst write, 32-bit address and data symbol parameter min max unit t 1 shared signal input setup time 7 ? ns t 2 shared signal input hold time 0 ? ns t 3 clk to shared signal output valid 2 11 ns t 10 clk high to gpio1_master/ high ? 20 ns
6-32 electrical specifications figure 6.21 burst write, 32-bit address and data t 1 clk (driven by system) gpio0_fetch/ (driven by LSI53C875A) gpio1_master/ (driven by LSI53C875A) req/ (driven by LSI53C875A) pa r (driven by LSI53C875A) irdy/ (driven by LSI53C875A) trdy/ (driven by target) stop/ (driven by target) devsel/ (driven by target) ad (driven by LSI53C875A) c_be/ (driven by LSI53C875A) t 3 cmd gnt/ (driven by arbiter) frame/ (driven by LSI53C875A) addr out t 2 be data out data out t 10 t 1 t 2
pci and external memory interface timing diagrams 6-33 table 6.28 burst write, 64-bit address and 32-bit data symbol parameter min max unit t 1 shared signal input setup time 7 ? ns t 2 shared signal input hold time 0 ? ns t 3 clk to shared signal output valid 2 11 ns t 10 clk high to gpio1_master/ high ? 20 ns
6-34 electrical specifications figure 6.22 burst write, 64-bit address and 32-bit data t 1 clk (driven by system) gpio0_fetch/ (driven by LSI53C875A) gpio1_master/ (driven by LSI53C875A) req/ (driven by LSI53C875A) pa r (driven by LSI53C875A) irdy/ (driven by LSI53C875A) trdy/ (driven by target) stop/ (driven by target) devsel/ (driven by target) ad[31:0] (driven by LSI53C875A) c_be[3:0]/ (driven by LSI53C875A) gnt/ (driven by arbiter) frame/ (driven by LSI53C875A) addr out lo t 2 addr out hi t 10 bus dual addr cmd data out data out be be t 3 t 1 t 2
pci and external memory interface timing diagrams 6-35 6.4.3 external memory timing the tables and figures in this section describe LSI53C875A external timings. the external memory write timings start on page 6-40 . table 6.29 external memory read symbol parameter min max unit t 1 shared signal input setup time 7 ? ns t 2 shared signal input hold time 0 ? ns t 3 clk to shared signal output valid ? 11 ns t 11 address setup to mas/ high 25 ? ns t 12 address hold from mas/ high 15 ? ns t 13 mas/ pulse width 25 ? ns t 14 mce/lowtodataclockedin 150 ? ns t 15 address valid to data clocked in 205 ? ns t 16 moe/lowtodataclockedin 100 ? ns t 17 data hold from address, moe/, mce/ change 0 ? ns t 19 data setup to clk high 5 ? ns
6-36 electrical specifications figure 6.23 external memory read 12 3 4 56 7 8 9 clk (driven by system) pa r (driven by master-addr; irdy/ (driven by master) trdy/ (driven by LSI53C875A) stop/ (driven by LSI53C875A) devsel/ (driven by LSI53C875A) ad (driven by master-addr; c_be[3:0]/ (driven by master) frame/ (driven by master) LSI53C875A-data) LSI53C875A-data) mad (addr driven by LSI53C875A; data driven by memory) mas1/ (driven by LSI53C875A) mas0/ (driven by LSI53C875A) mwe/ (driven by LSI53C875A) moe/ (driven by LSI53C875A) mce/ (driven by LSI53C875A) in cmd addr in t 1 t 2 t 13 t 12 t 11 byte enable t 1 t 1 t 2 t 2 t 3 t 1 t 2 t 1 upper address middle address lower address
pci and external memory interface timing diagrams 6-37 figure 6.23 external memory read (cont.) mad (addr driven by LSI53C875A; data driven by memory) 11 12 13 14 15 16 17 18 19 20 21 10 clk (driven by system) pa r (driven by master-addr; irdy/ (driven by master) trdy/ (driven by LSI53C875A) stop/ (driven by LSI53C875A) devsel/ (driven by LSI53C875A) ad (driven by master-addr; c_be[3:0]/ (driven by master) frame/ (driven by master) LSI53C875A-data) LSI53C875A-data) mas1/ (driven by LSI53C875A) mas0/ (driven by LSI53C875A) mwe/ (driven by LSI53C875A) moe/ (driven by LSI53C875A) mce/ (driven by LSI53C875A) out data data out byte enable lower address t 3 t 3 t 2 t 2 t 3 t 3 t 19 t 17 t 15 t 14 t 16 in 9
6-38 electrical specifications table 6.30 external memory write symbol parameter min max unit t 1 shared signal input setup time 7 ? ns t 2 shared signal input hold time 0 ? ns t 3 clk to shared signal output valid ? 11 ns t 11 address setup to mas/ high 25 ? ns t 12 address hold from mas/ high 15 ? ns t 13 mas/ pulse width 25 ? ns t 20 data setup to mwe/ low 30 ? ns t 21 data hold from mwe/ high 20 ? ns t 22 mwe/ pulse width 100 ? ns t 23 address setup to mwe/ low 60 ? ns t 24 mce/ low to mwe/ high 120 ? ns t 25 mce/ low to mwe/ low 25 ? ns t 26 mwe/ high to mce/ high 25 ? ns
pci and external memory interface timing diagrams 6-39 the external memory write timings start on page 6-40 .
6-40 electrical specifications figure 6.24 external memory write 12 34 5 6 78 9 clk (driven by system) pa r (driven by master-addr; irdy/ (driven by master) trdy/ (driven by LSI53C875A) stop/ (driven by LSI53C875A) devsel/ (driven by LSI53C875A) ad (driven by master-addr; c_be[3:0]/ (driven by master) frame/ (driven by master) LSI53C875A-data) LSI53C875A-data) mad (addr driven by LSI53C875A; data driven by memory) mas1/ (driven by LSI53C875A) mas0/ (driven by LSI53C875A) mwe/ (driven by LSI53C875A) moe/ (driven by LSI53C875A) mce/ (driven by LSI53C875A) in cmd addr in t 1 t 2 t 13 t 12 t 11 byte enable t 1 t 1 t 2 t 2 t 3 t 1 t 2 t 1 higher address middle address lower address t 1
pci and external memory interface timing diagrams 6-41 figure 6.24 external memory write (cont.) mad (addr driven by LSI53C875A; data driven by memory) 11 12 13 14 15 16 17 18 19 20 21 10 clk (driven by system) pa r (driven by master-addr; irdy/ (driven by master) trdy/ (driven by LSI53C875A) stop/ (driven by LSI53C875A) devsel/ (driven by LSI53C875A) ad (driven by master-addr; c_be[3:0]/ (driven by master) frame/ (driven by master) LSI53C875A-data) LSI53C875A-data) mas1/ (driven by LSI53C875A) mas0/ (driven by LSI53C875A) mwe/ (driven by LSI53C875A) moe/ (driven by LSI53C875A) mce/ (driven by LSI53C875A) in byte enable lower address t 2 t 1 t 2 t 2 t 3 t 3 t 24 data in t 2 t 25 t 20 t 26 t 21 t 22 t 23 9 data out
6-42 electrical specifications figure 6.25 normal/fast memory ( = 128 kbytes) single byte access read cycle table 6.31 normal/fast memory ( = 128 kbytes) single byte access read cycle symbol parameter min max unit t 11 address setup to mas/ high 25 ? ns t 12 address hold from mas/ high 15 ? ns t 13 mas/ pulse width 25 ? ns t 14 mce/ low to data clocked in 150 ? ns t 15 address valid to data clocked in 205 ? ns t 16 moe/ low to data clocked in 100 ? ns t 17 data hold from address, moe/, mce/ change 0 ? ns t 18 address out from moe/, mce/ high 50 ? ns t 19 data setup to clk high 5 ? ns clk mad (addr driven by LSI53C875A; data driven by memory) mas1/ (driven by LSI53C875A) mas0/ (driven by LSI53C875A) mce/ (driven by LSI53C875A) moe/ (driven by LSI53C875A) mwe/ (driven by LSI53C875A) t 11 t 12 t 13 t 15 t 14 t 16 t 18 t 17 t 19 higher address 1. 2. 3. 1. middle address 2. lower address 3. valid read data
pci and external memory interface timing diagrams 6-43 figure 6.26 normal/fast memory ( = 128 kbytes) single byte access write cycle table 6.32 normal/fast memory ( = 128 kbytes) single byte access write cycle symbol parameter min max unit t 11 address setup to mas/ high 25 ? ns t 12 address hold from mas/ high 15 ? ns t 13 mas/ pulse width 25 ? ns t 20 data setup to mwe/ low 30 ? ns t 21 data hold from mwe/ high 20 ? ns t 22 mwe/ pulse width 100 ? ns t 23 address setup to mwe/ low 60 ? ns t 24 mce/ low to mwe/ high 120 ? ns t 25 mce/ low to mwe/ low 25 ? ns t 26 mwe/ high to mce/ high 25 ? ns clk mad (driven by LSI53C875A) mas1/ (driven by LSI53C875A) mas0/ (driven by LSI53C875A) mce/ (driven by LSI53C875A) moe/ (driven by LSI53C875A) mwe/ (driven by LSI53C875A) t 11 t 12 t 13 t 23 t 24 t 20 higher address 1. 2. 1. middle address 2. lower address valid write data t 22 t 21 t 26 t 25
6-44 electrical specifications figure 6.27 normal/fast memory ( = 128 kbytes) multiple byte access read cycle mad (addr driven by LSI53C875A; mas1/ (driven by LSI53C875A) mas0/ (driven by LSI53C875A) mce/ (driven by LSI53C875A) moe/ (driven by LSI53C875A) mwe/ (driven by LSI53C875A) 02 4 6 81012 141617 data driven by memory) clk (driven by system) pa r (driven by LSI53C875A- irdy/ (driven by master) trdy/ (driven by LSI53C875A) stop/ (driven by LSI53C875A) devsel/ (driven by LSI53C875A) ad (driven by LSI53C875A- c_be[3:0]/ (driven by master) frame/ (driven by master) master-addr; data) master-addr; data) byte enable addr in cmd upper address middle address lower address in
pci and external memory interface timing diagrams 6-45 figure 6.27 normal/fast memory ( = 128 kbytes) multiple byte access read cycle (cont.) mad (addr driven by LSI53C875A ; mas1/ (driven by LSI53C875A) mas0/ (driven by LSI53C875A) mce/ (driven by LSI53C875A) moe/ (driven by LSI53C875A) mwe/ (driven by LSI53C875A) 15 18 20 22 24 26 28 30 data driven by memory) clk (driven by system) pa r (driven by LSI53C875A- irdy/ (driven by master) trdy/ (driven by LSI53C875A) stop/ (driven by LSI53C875A) devsel/ (driven by LSI53C875A) ad (driven by LSI53C875A- c_be[3:0]/ (driven by master) frame/ (driven by master) master-addr; data) master-addr; data) 16 32 data in byte enable out data in lower address data in
6-46 electrical specifications figure 6.28 normal/fast memory ( = 128 kbytes) multiple byte access write cycle mad (driven by LSI53C875A) mas1/ (driven by LSI53C875A) mas0/ (driven by LSI53C875A) mce/ (driven by LSI53C875A) moe/ (driven by LSI53C875A) mwe/ (driven by LSI53C875A) 02468101214 clk (driven by system) pa r (driven by master-addr; irdy/ (driven by master) trdy/ (driven by LSI53C875A) stop/ (driven by LSI53C875A) devsel/ (driven by LSI53C875A) ad (driven by master-addr; c_be[3:0]/ (driven by master) frame/ (driven by master) LSI53C875A-data) LSI53C875A-data) byte enable addr in cmd upper address middle address lower address data in in
pci and external memory interface timing diagrams 6-47 figure 6.28 normal/fast memory ( = 128 kbytes) multiple byte access write cycle (cont.) mad (driven by LSI53C875A; mas1/ (driven by LSI53C875A) mas0/ (driven by LSI53C875A) mce/ (driven by LSI53C875A) moe/ (driven by LSI53C875A) mwe/ (driven by LSI53C875A) 15 18 20 22 24 26 28 30 clk (driven by system) pa r (driven by master-addr; irdy/ (driven by master) trdy/ (driven by LSI53C875A) stop/ (driven by LSI53C875A) devsel/ (driven by LSI53C875A) ad (driven by master-addr; c_be[3:0]/ (driven by master) frame/ (driven by master) LSI53C875A-data) LSI53C875A-data) 16 32 data in byte enable data out lower address data out in
6-48 electrical specifications figure 6.29 slow memory ( = 128 kbytes) read cycle table 6.33 slow memory ( = 128 kbytes) read cycle symbol parameter min max unit t 11 address setup to mas/ high 25 ? ns t 12 address hold from mas/ high 15 ? ns t 13 mas/ pulse width 25 ? ns t 14 mce/ low to data clocked in 150 ? ns t 15 address valid to data clocked in 205 ? ns t 16 moe/ low to data clocked in 100 ? ns t 17 data hold from address, moe/, mce/ change 0 ? ns t 18 address out from moe/, mce/ high 50 ? ns t 19 data setup to clk high 5 ? ns t 14 t 18 t 19 t 17 t 11 t 12 t 13 t 15 t 16 clk mas1/ (driven by LSI53C875A) mas0/ (driven by LSI53C875A) mce/ (driven by LSI53C875A) moe/ (driven by LSI53C875A) mwe/ (driven by LSI53C875A) mad (address driven by LSI53C875A; data driven by memory) higher address middle address lower address valid read data
pci and external memory interface timing diagrams 6-49 figure 6.30 slow memory ( = 128 kbytes) write cycle table 6.34 slow memory ( 128 kbytes) write cycle symbol parameter min max unit t 11 address setup to mas/ high 25 ? ns t 12 address hold from mas/ high 15 ? ns t 13 mas/ pulse width 25 ? ns t 20 data setup to mwe/ low 30 ? ns t 21 data hold from mwe/ high 20 ? ns t 22 mwe/ pulse width 100 ? ns t 23 address setup to mwe/ low 60 ? ns t 24 mce/ low to mwe/ high 120 ? ns t 25 mce/ low to mwe/ low 25 ? ns t 26 mwe/ high to mce/ high 25 ? ns clk mad (driven by LSI53C875A) mas1/ (driven by LSI53C875A) mas0/ (driven by LSI53C875A) mce/ (driven by LSI53C875A) moe/ (driven by LSI53C875A) mwe/ (driven by LSI53C875A) higher address lower address t 12 middle address valid write data t 11 t 13 t 21 t 22 t 20 t 23 t 24 t 25 t 26
6-50 electrical specifications figure 6.31 64 kbytes rom read cycle table 6.35 = 64 kbytes rom read cycle symbol parameter min max unit t 11 address setup to mas/ high 25 ? ns t 12 address hold from mas/ high 15 ? ns t 13 mas/ pulse width 25 ? ns t 14 mce/ low to data clocked in 150 ? ns t 15 address valid to data clocked in 205 ? ns t 16 moe/lowtodataclockedin 100 ? ns t 17 data hold from address, moe/, mce/ change 0 ? ns t 18 address out from moe/, mce/ high 50 ? ns t 19 data setup to clk high 5 ? ns clk mad (address driven by LSI53C875A; data driven by memory) mas1/ (driven by LSI53C875A) mas0/ (driven by LSI53C875A) mce/ (driven by LSI53C875A) moe/ (driven by LSI53C875A) mwe/ (driven by LSI53C875A) higher address lower address valid read data t 17 t 12 t 15 t 14 t 18 t 16 t 19 t 11 t 13
pci and external memory interface timing diagrams 6-51 figure 6.32 64 kbyte rom write cycle table 6.36 = 64 kbyte rom write cycle symbol parameter min max unit t 11 address setup to mas/ high 25 ? ns t 12 address hold from mas/ high 15 ? ns t 13 mas/ pulse width 25 ? ns t 20 data setup to mwe/ low 30 ? ns t 21 data hold from mwe/ high 20 ? ns t 22 mwe/ pulse width 100 ? ns t 23 address setup to mwe/ low 60 ? ns t 24 mce/ low to mwe/ high 120 ? ns t 25 mce/ low to mwe/ low 25 ? ns t 26 mwe/ high to mce/ high 25 ? ns clk mad (driven by LSI53C875A) mas1/ (driven by LSI53C875A) mas0/ (driven by LSI53C875A) mce/ (driven by LSI53C875A) moe/ (driven by LSI53C875A) mwe/ (driven by LSI53C875A) higher address lower address valid write data t 11 t 12 t 13 t 24 t 25 t 20 t 23 t 22 t 26 t 21
6-52 electrical specifications 6.5 scsi timing diagrams the tables and diagrams in this section describe the LSI53C875A scsi timings. figure 6.33 initiator asynchronous send table 6.37 initiator asynchronous send symbol parameter min max unit t 1 sack/ asserted from sreq/ asserted 5 ? ns t 2 sack/ deasserted from sreq/ deasserted 5 ? ns t 3 data setup to sack/ asserted 55 ? ns t 4 data hold from sreq/ deasserted 0 ? ns sreq/ sack/ sd[15:0]/ sdp[1:0]/ t 1 t 2 t 3 t 4 n+1 n valid n valid n + 1 n+1
scsi timing diagrams 6-53 figure 6.34 initiator asynchronous receive table 6.38 initiator asynchronous receive symbol parameter min max unit t 1 sack/ asserted from sreq/ asserted 5 ? ns t 2 sack/ deasserted from sreq/ deasserted 5 ? ns t 3 data setup to sreq/ asserted 0 ? ns t 4 data hold from sack/ asserted 0 ? ns sreq/ sack/ sd[15:0]/, sdp[1:0]/ t 1 t 2 n+1 validn+1 valid n n t 3 t 4 n n+1
6-54 electrical specifications figure 6.35 target asynchronous send table 6.39 target asynchronous send symbol parameter min max unit t 1 sreq/ deasserted from sack/ asserted 5 ? ns t 2 sreq/ asserted from sack/ deasserted 5 ? ns t 3 data setup to sreq/ asserted 55 ? ns t 4 data hold from sack/ asserted 0 ? ns sreq/ sack/ sd[15:0]/, sdp[1:0]/ t 3 t 2 t 1 valid n valid n + 1 n+1 n t 4 n+1 n
scsi timing diagrams 6-55 figure 6.36 target asynchronous receive table 6.40 target asynchronous receive symbol parameter min max unit t 1 sreq/ deasserted from sack/ asserted 5 ? ns t 2 sreq/ asserted from sack/ deasserted 5 ? ns t 3 data setup to sack/ asserted 0 ? ns t 4 data hold from sreq/ deasserted 0 ? ns table 6.41 scsi-1 transfers (5.0 mbytes) symbol parameter min max unit t 1 send sreq/ or sack/ assertion pulse width 80 ? ns t 2 send sreq/ or sack/ deassertion pulse width 80 ? ns t 1 receive sreq/ or sack/ assertion pulse width 70 ? ns t 2 receive sreq/ or sack/ deassertion pulse width 70 ? ns t 3 send data setup to sreq/ or sack/ asserted 24 ? ns t 4 send data hold from sreq/ or sack/ asserted 54 ? ns t 5 receive data setup to sreq/ or sack/ asserted 14 ? ns t 6 receive data hold from sreq/ or sack/ asserted 24 ? ns sreq/ sack/ sd[15:0]/, sdp[1:0]/ n n+1 t 2 t 1 t 3 t 4 valid n valid n + 1 n+1 n
6-56 electrical specifications table 6.42 scsi-2 fast transfers 10.0 mbytes (8-bit transfers) or 20.0 mbytes (16-bit transfers) 40 mhz clock symbol parameter min max unit t 1 send sreq/ or sack/ assertion pulse width 30 ? ns t 2 send sreq/ or sack/ deassertion pulse width 30 ? ns t 1 receive sreq/ or sack/ assertion pulse width 22 ? ns t 2 receive sreq/ or sack/ deassertion pulse width 22 ? ns t 3 send data setup to sreq/ or sack/ asserted 24 ? ns t 4 send data hold from sreq/ or sack/ asserted 34 ? ns t 5 receive data setup to sreq/ or sack/ asserted 14 ? ns t 6 receive data hold from sreq/ or sack/ asserted 24 ? ns table 6.43 ultra scsi transfers 20.0 mbytes (8-bit transfers) or 40.0 mbytes (16-bit transfers) quadrupled 40 mhz clock 1, 2 1. transfer period bits (bits [6:4] in the scsi transfer (sxfer) register)aresettozeroandtheextra clock cycle of data setup bit (bit 7 in scsi control one (scntl1) )isset. 2. during ultra scsi transfers, the value of the extend req/ack filtering bit ( scsi test two (stest2) , bit 1) has no effect. symbol parameter min max unit t 1 send sreq/ or sack/ assertion pulse width 15 ? ns t 2 send sreq/ or sack/ deassertion pulse width 15 ? ns t 1 receive sreq/ or sack/ assertion pulse width 11 ? ns t 2 receive sreq/ or sack/ deassertion pulse width 11 ? ns t 3 send data setup to sreq/ or sack/ asserted 12 ? ns t 4 send data hold from sreq/ or sack/ asserted 17 ? ns t 5 receive data setup to sreq/ or sack/ asserted 6 ? ns t 6 receive data hold from sreq/ or sack/ asserted 11 ? ns
scsi timing diagrams 6-57 figure 6.37 initiator and target synchronous transfer sreq/ or sack/ send data sd[15:0]/, sdp[1:0]/ receive data sd[15:0]/, sdp[1:0]/ t 3 t 4 t 1 t 2 t 5 t 6 nn+1 valid n valid n + 1 valid n valid n + 1
6-58 electrical specifications 6.6 package diagrams this section of the manual has a package drawing and pinout for both the pqfp and bga. figure 6.38 LSI53C875A 160-pin pqfp mechanical drawing important: this drawing may not be the latest version. for board layout and manufacturing, obtain the most recent engineering drawings from your lsi logic marketing representative by requesting the outline drawing for package code p3.
package diagrams 6-59 figure 6.38 160-pin pqfp (p3) mechanical drawing (sheet 2 of 2) important: this drawing may not be the latest version. for board layout and manufacturing, obtain the most recent engineering drawings from your lsi logic marketing representative by requesting the outline drawing for package code p3.
6-60 electrical specifications table 6.44 160 pqfp pin list by location nc 121 nc 122 vssio 123 nc 124 nc 125 test_hsc/ 126 test_rst/ 127 vddio 128 vdda 129 tck 130 trst/ 131 vssa 132 vssio 133 nc 134 nc 135 masn[1]/ 136 masn[0]/ 137 vddio 138 mew/ 139 moe/ 140 mce/ 141 tdi 142 serr/ 143 rst/ 144 clk 145 vsscore 146 gnt/ 147 req/ 148 vddcore 149 pci_ad[31] 150 pci_ad[30] 151 vssio 152 pci_ad[29] 153 pci_ad[28] 154 vddio 155 pci_ad[27] 156 pci_ad[26] 157 vssio 158 pci_ad[25] 159 pci_ad[24] 160 signal pin signal pin c_be[3]/ 1 idsel 2 pci_ad[23] 3 vssio 4 pci_ad[22] 5 pci_ad[21] 6 pci_ad[20] 7 vddio 8 pci_ad[19] 9 vssio 10 pci_ad[18] 11 pci_ad[17] 12 pci_ad[16] 13 vssio 14 c_ben[2] 15 frame/ 16 irdy/ 17 vssio 18 trdy/ 19 devsel/ 20 vddio 21 stop/ 22 vssio 23 perr/ 24 pa r 2 5 c_ben[1]/ 26 vssio 27 pci_ad[15] 28 pci_ad[14] 29 pci_ad[13] 30 vssio 31 pci_ad[12] 32 vddio 33 pci_ad[11] 34 pci_ad[10] 35 pci_ad[9] 36 vssio 37 pci_ad[8] 38 c_ben[0]/ 39 pci_ad[7] 40 pci_ad[6] 41 vssio 42 pci_ad[5] 43 pci_ad[4] 44 vddio 45 pci_ad[3] 46 pci_ad[2] 47 vssio 48 pci_ad[1] 49 pci_ad[0] 50 vddcore 51 irq/ 52 gpio[0] 53 gpio[1] 54 vsscore 55 sclk 56 tms/ 57 tdo/ 58 mad[7] 59 mad[6] 60 mad[5] 61 mad[4] 62 vddio 63 mad[3] 64 mad[2] 65 mad[1] 66 mad[0] 67 gpio[2] 68 vssio 69 gpio[3] 70 gpio[4] 71 nc 1 72 nc 73 vddio 74 nc 75 nc 76 macn_testout 77 nc 78 vssio 79 vsscore 80 nc 81 nc 82 vddcore 83 vddscsi 84 sd[11]/ 85 sd[10]/ 86 sd[9]/ 87 vssio 88 sd[8]/ 89 io/ 90 req/ 91 cd/ 92 vsssio 93 sel/ 94 msg/ 95 rst/ 96 ack/ 97 bsy/ 98 vssio 99 atn/ 100 sdp[0]/ 101 sd[7]/ 102 sd[6]/ 103 vssio 104 sd[5]/ 105 sd[4]/ 106 sd[3]/ 107 sd[2]/ 108 vssio 109 sd[1]/ 110 sd[0]/ 111 sdp[1]/ 112 sd[15]/ 113 vssio 114 sd[14]/ 115 sd[13]/ 116 sd[12]/ 117 vddio 118 nc 119 nc 120 signal pin signal pin 1. nc pins are not connected.
package diagrams 6-61 figure 6.39 169-pin bga mechanical drawing important: this drawing may not be the latest version. for board layout and manufacturing, obtain the most recent engineering drawings from your lsi logic marketing representative by requesting the outline drawing for package code gv.
6-62 electrical specifications table 6.45 169 bga pin list by location vssio k12 sio k13 pci_ad[9] l1 pci_ad[8] l2 pci_ad[4] l3 pci_ad[2] l4 vddcore l5 vsscore l6 mad[7] l7 mad[1] l8 gpio[4] l9 mac_testout/ l10 vddio l11 vddcore l12 sd[10] l13 pci_ad[7] m1 nc m2 pci_ad[5] m3 nc m4 irq/ m5 sclk m6 mad[6] m7 mad[3] m8 gpio[3] m9 vddio m10 nc m11 nc m12 nc m13 pci_ad[6] n1 nc n2 pci_ad[3] n3 pci_ad[0] n4 gpio[0] n5 tms n6 mad[5] n7 mad[2] n8 vssio n9 nc n10 nc n11 vsscore n12 nc n13 signal pin signal pin c_be[3]/ a1 pci_ad[24] a2 pci_ad[27] a3 pci_ad[29] a4 vddcore a5 clk a6 mce/ a7 mas[0]/ a8 vssio a9 tck a10 test_hsc/ a11 nc 1 a12 nc a13 idsel b1 nc b2 nc b3 pci_ad[28] b4 pci_ad[31] b5 rst/ b6 moe/ b7 mas[1]/ b8 vssa b9 vddio b10 vssio b11 nc b12 nc b13 pci_ad[21] c1 pci_ad[23] c2 nc c3 pci_ad[26] c4 pci_ad[30] c5 vsscore c6 mwe/ c7 nc c8 trst/ c9 test_rst/ c10 nc c11 vddio c12 sd[13] c13 nc d1 vddpci1 d2 pci_ad[20]d3 pci_ad[25] d4 vddio d5 gnt/ d6 tdi d7 nc d8 vdda d9 nc d10 sd[12] d11 vssio d12 sd[15] d13 pci_ad[16] e1 pci_ad[17] e2 pci_ad[18] e3 pci_ad[19] e4 pci_ad[22] e5 req/ e6 serr/ e7 vddio e8 nc e9 sd[14] e10 sd[0] e11 sd[1] e12 vssio e13 irdy/ f1 frame/ f2 c_be[2]/ f3 nc f4 nc f5 nc f6 sdp[1] f8 sd[2] f9 sd[3] f10 sd[4] f11 vssio f12 sd[5] f13 vddio g1 devsel/ g2 trdy/ g3 stop/ g4 nc g5 sd[6]g9 sd[7] g10 vssio g11 at n / g 1 2 sdp[0] g13 pa r h 1 perr/ h2 c_be[1]/ h3 nc h4 pci_ad[15] h5 pci_ad[12] h6 nc h8 sbsy h9 ssel h10 smsg h11 srst h12 sack h13 pci_ad[14] j1 pci_ad[13] j2 nc j3 pci_ad[10] j4 vddio j5 tdo j6 vddio j7 gpio[2] j8 sd[11] j9 sd[8] j10 sreq j11 scd j12 vssio j13 vddio k1 pci_ad[11] k2 nc k3 c_be[0]/ k4 pci_ad[1] k5 gpio[1] k6 mad[4] k7 mad[0] k8 nc k9 vssio k10 sd[9] k11 signal pin signal pin 1. nc pins are not connected.
LSI53C875A pci to ultra scsi controller a-1 appendix a register summary table a.1 LSI53C875A pci register map register name address read/write page base address register one (memory) 0x14?0x17 read/write 4-9 base address register two (scripts ram) 0x18?0x1b read/write 4-10 base address register zero (i/o) 0x10?0x13 read/write 4-9 bridge support extensions (pmcsr_bse) 0x46 read only 4-17 cache line size 0x0c read/write 4-7 capabilities pointer 0x34 read only 4-13 capability id 0x40 read only 4-15 class code 0x09?0x0b read only 4-7 command 0x04?0x05 read/write 4-3 data 0x47 read only 4-18 device id 0x02?0x03 read only 4-3 expansion rom base address 0x30?0x33 read/write 4-12 header type 0x0e read only 4-8 interrupt line 0x3c read/write 4-13 interrupt pin 0x3d read only 4-14 latency timer 0x0d read/write 4-8 max_lat 0x3f read only 4-14 min_gnt 0x3e read only 4-14 next item pointer 0x41 read only 4-15
a-2 register summary power management capabilities (pmc) 0x42?0x43 read only 4-15 power management control/status (pmcsr) 0x44?0x45 read/write 4-16 reserved 0x28?0x2b ? 4-10 reserved 0x35?0x3b ? 4-13 revision id (rev id) 0x08 read only 4-6 status 0x06?0x07 read/write 4-5 subsystem id 0x2e?0x2f read only 4-11 subsystem vendor id 0x2c?0x2d read only 4-10 vendor id 0x00?0x01 read only 4-2 table a.2 LSI53C875A scsi register map register name address read/write page adder sum output (adder) 0x3c?0x3f read only 4-73 chip control 0 (ccntl0) 0x56 read/write 4-95 chip control 1 (ccntl1) 0x57 read/write 4-97 chip test five (ctest5) 0x22 read/write 4-60 chip test four (ctest4) 0x21 read/write 4-59 chip test one (ctest1) 0x19 read only 4-53 chip test six (ctest6) 0x23 read/write 4-62 chip test three (ctest3) 0x1b read/write 4-56 c h i p te s t tw o ( c t e s t 2 ) 0 x 1 a r e a d o n l y ( b i t 3 w r i t e ) 4 - 5 4 chip test zero (ctest0) 0x18 read/write 4-53 cumulative scsi byte count (csbc) 0xdc?0xdf read/write 4-108 data structure address (dsa) 0x10?0x13 read/write 4-47 dma byte counter (dbc) 0x24?0x26 read/write 4-62 table a.1 LSI53C875A pci register map (cont.) register name address read/write page
register summary a-3 dma command (dcmd) 0x27 read/write 4-63 dma control (dcntl) 0x3b read/write 4-70 dma fifo (dfifo) 0x20 read/write 4-57 dma interrupt enable (dien) 0x39 read/write 4-69 dma mode (dmode) 0x38 read/write 4-66 dma next address (dnad) 0x28?0x2b read/write 4-64 dma next address 64 (dnad64) 0xb8?0xbb read/write 4-103 dma scripts pointer (dsp) 0x2c?0x2f read/write 4-64 dma scripts pointer save (dsps) 0x30?0x33 read/write 4-65 dma status (dstat) 0x0c read only 4-39 dsa relative selector (drs) 0xac?0xaf read/write 4-101 dynamic block move selector (dbms) 0xb4?0xb7 read/write 4-103 entry storage address (esa) 0xd0?0xd3 read/write 4-106 general purpose (gpreg0) 0x07 read/write 4-35 general purpose pin control zero (gpcntl0) 0x47 read/write 4-82 instruction address (ia) 0xd4?0xd7 read/write 4-107 interrupt status one (istat1) 0x15 read/write 4-51 interrupt status zero (istat0) 0x14 read/write 4-48 mailbox one (mbox1) 0x17 read/write 4-52 mailbox zero (mbox0) 0x16 read/write 4-52 memory access control (macntl) 0x46 read/write 4-81 memory move read selector (mmrs) 0xa0?0xa3 read/write 4-100 memory move write selector (mmws) 0xa4?0xa7 read/write 4-100 phase mismatch jump address 1 (pmjad1) 0xc0?0xc3 read/write 4-104 phase mismatch jump address 2 (pmjad2) 0xc4?0xc7 read/write 4-104 table a.2 LSI53C875A scsi register map (cont.) register name address read/write page
a-4 register summary remaining byte count (rbc) 0xc8?0xcb read/write 4-105 reserved 0x53 ? 4-94 reserved 0x5a?0x5b ? 4-99 reserved 0xbc?0xbf ? 4-103 reserved 0xdb ? 4-108 reserved 0xe0?0xff ? 4-108 response id one (respid1) 0x4b read/write 4-86 response id zero (respid0) 0x4a read/write 4-86 scratch byte register (sbr) 0x3a read/write 4-70 scratch register a (scratcha) 0x34?0x37 read/write 4-65 scratch register b (scratchb) 0x5c?0x5f read/write 4-99 scratch registers c?r (scratchc?scratchr) 0x60?0x9f read/write 4-99 scripts fetch selector (sfs) 0xa8?0xab read/write 4-101 scsi bus control lines (sbcl) 0x0b read only 4-38 scsi bus data lines (sbdl) 0x58?0x59 read only 4-98 scsi byte count (sbc) 0xd8?0xda read only 4-107 scsi chip id (scid) 0x04 read/write 4-30 scsi control one (scntl1) 0x01 read/write 4-23 scsi control three (scntl3) 0x03 read/write 4-28 scsi control two (scntl2) 0x02 read/write 4-26 scsi control zero (scntl0) 0x00 read/write 4-20 scsi destination id (sdid) 0x06 read/write 4-35 scsi first byte received (sfbr) 0x08 read/write 4-36 scsi input data latch (sidl) 0x50?0x51 read only 4-93 scsi interrupt enable one (sien1) 0x41 read/write 4-75 table a.2 LSI53C875A scsi register map (cont.) register name address read/write page
register summary a-5 scsi interrupt enable zero (sien0) 0x40 read/write 4-73 scsi interrupt status one (sist1) 0x43 read only 4-78 scsi interrupt status zero (sist0) 0x42 read only 4-76 scsi longitudinal parity (slpar) 0x44 read/write 4-79 scsi output control latch (socl) 0x09 read/write 4-37 scsi output data latch (sodl) 0x54?0x55 read/write 4-94 scsi selector id (ssid) 0x0a read only 4-38 scsi status one (sstat1) 0x0e read only 4-43 scsi status two (sstat2) 0x0f read only 4-46 scsi status zero (sstat0) 0x0d read only 4-42 scsi test four (stest4) 0x52 read only 4-94 scsi test one (stest1) 0x4d read/write 4-88 scsi test three (stest3) 0x4f read/write 4-91 scsi test two (stest2) 0x4e read/write 4-89 scsi test zero (stest0) 0x4c read only 4-87 scsi timer one (stime1) 0x49 read/write 4-85 scsi timer zero (stime0) 0x48 read/write 4-83 scsi transfer (sxfer) 0x05 read/write 4-31 scsi wide residue (swide) 0x45 read/write 4-81 static block move selector (sbms) 0xb0?0xb3 read/write 4-102 temporary (temp) 0x1c?0x1f read/write 4-57 updated address (ua) 0xcc?0xcf read/write 4-105 table a.2 LSI53C875A scsi register map (cont.) register name address read/write page
a-6 register summary
LSI53C875A pci to ultra scsi controller b-1 appendix b external memory interface diagram examples appendix b has example external memory interface diagrams. figure b.1 16 kbyte interface with 200 ns memory LSI53C875A 27c128 moe/ oe mce/ ce d0 8 mad[7:0] bus ck q0 8 a[7:0] qe 6 a[13:8] v dd mas0/ mas1/ note: mad[3:1] pulled low internally. mad bus sense logic enabled for 16 kbyte of slow memory (200 ns devices @ 33 mhz). hct374 d[7:0] mad0 4.7 k d7 q7 d0 ck q0 qe hct374 d5 q5
b-2 external memory interface diagram examples figure b.2 64 kbyte interface with 150 ns memory LSI53C875A 27c512-15/ moe/ oe mce/ ce d0 8 mad[7:0] bus ck q0 8 a[7:0] qe 6 a[15:8] v dd mas0/ mas1/ note: mad 3, 1, 0 pulled low internally. mad bus sense logic enabled for 64 kbyte of fast memory (150 ns devices @ 33 mhz). hct374 gpio4 mwe/ vpp control +12v vpp we optional - for flash memory only, not required for eeproms. 28f512-15/ socket d[7:0] mad2 4.7 k d7 q7 d0 ck q0 qe hct374 d7 q7
external memory interface diagram examples b-3 figure b.3 128 kbytes, 256 kbytes, 512 kbytes, or 1 mbyte interface with 150 ns memory LSI53C875A 27c020-15/ moe/ oe mce/ ce 8 mad[7:0] bus 8 a[7:0] 6 a[15:8] v dd mas0/ mas1/ note: mad[2:0] pulled low internally. mad bus sense logic enabled for 128, 256, 512 kbytes, or 1 mbyte of fast memory (150 ns devices @ 33 mhz). the hct374s may be replaced with hct377s. gpio4 mwe/ vpp control +12v vpp we optional - for flash memory only, not required for eeproms. 28f020-15/ socket d[7:0] mad3 4.7 k d0 ck q0 q3 4 hct377 mad[3:0] bus e a[19:16] d0 ck q0 qe hct374 d7 q7 d0 ck q0 qe hct374 d7 q7 d3
b-4 external memory interface diagram examples figure b.4 512 kbyte interface with 150 ns memory oe we d[7:0] a0 a16 . . . LSI53C875A moe/ 8 mad[7:0] bus a[7:0] d0 ck q0 qe 8 a[15:8] v dd mas0/ mas1/ note: mad2 pulled low internally. mad bus sense logic enabled for 512 kbytes of slow memory (150 ns devices, additional time required for hct139 @ 33 mhz). the hct374s may be replaced with hct377s. hct374 gpio4 mwe/ vpp control +12v vpp optional - for flash memory only, not required for eeproms. d[7:0] mad3 4.7 k d0 ck q0 q2 3 hct377 mad[2:0] bus e mad1 4.7 k mad3 4.7 k a b gb y0 y1 y2 y3 mce/ hct139 ce ce ce ce 27c010-15/28f010-15 sockets d2 d7 q7 d0 ck q0 qe hct374 d7 q7 oe we d[7:0] a0 a16 . . . oe we d[7:0] a0 a16 . . . oe we d[7:0] a0 a16 . . .
LSI53C875A pci to ultra scsi controller ix-1 index symbols (64timod) 4-97 (a7) 5-23 (aap) 4-22 (abrt) 4-40 , 4-48 (ack) 4-37 , 4-39 (adb) 4-23 (adck) 4-60 (adder) 4-73 (aesp) 4-24 (aip) 4-43 (aps) 4-16 (arb[1:0]) 4-20 (art) 4-87 (atn) 4-37 , 4-39 (aws) 4-90 (bar0) 4-9 (bar1) 4-9 (bar2) 4-10 (bbck) 4-61 (bdis) 4-59 (bf) 4-40 , 4-69 (bl[1:0]) 4-66 (bl2) 4-61 (bo) 4-57 (bo[9:8]) 4-62 (bof) 4-68 (bse) 4-17 (bsy) 4-37 , 4-39 (c_d) 4-37 , 4-39 , 4-45 (cc) 4-7 (ccf[2:0]) 4-29 (ccntl0) 4-95 (ccntl1) 4-97 (chm) 4-26 (cid) 4-15 (cio) 4-54 (clf) 4-56 (cls) 4-7 (clse) 4-70 (cm) 4-54 (cmp) 4-74 , 4-77 (com) 4-72 (con) 4-24 , 4-49 (cp) 4-13 (csbc) 4-108 (csf) 4-92 (ctest0) 4-53 (ctest1) 4-53 (ctest2) 4-54 (ctest3) 4-56 (ctest4) 4-59 (ctest5) 4-60 (ctest6) 4-62 (d1s) 4-16 (d2s) 4-16 (dack) 4-55 (data) 4-18 (dbc) 4-62 (dbms) 4-103 (dcmd) 4-63 (dcntl) 4-70 (ddac) 4-97 (ddir) 4-54 , 4-61 (df) 4-62 (dfe) 4-39 (dfifo) 4-57 (dfs) 4-61 (dhp) 4-23 (did) 4-3 (dien) 4-69 (dils) 4-96 (diom) 4-67 (dip) 4-50 (dmode) 4-66 (dnad) 4-64 (dnad64) 4-103 (dpe) 4-5 (dpr) 4-6 (drd) 4-82 (dreq) 4-55 (drs) 4-102 (dsa) 4-47 (dscl) 4-17 (dsi) 4-16 , 4-92 (dslt) 4-17 (dsp) 4-64 (dsps) 4-65 (dstat) 4-39 (dt[1:0]) 4-5 (dwr) 4-82 (ebm) 4-4 (eis) 4-4 (ems) 4-4 (en64dbmv) 4-98 (en64tibmv) 4-98 (enc) 4-30 , 4-35 (enid) 4-38 (enndj) 4-96 (enpmj) 4-95 (epc) 4-22 (eper) 4-3
ix-2 index (erba) 4-12 (erl) 4-67 (ermp) 4-68 (esa) 4-106 (ews) 4-29 (exc) 4-23 (ext) 4-90 (fbl3) 4-59 (fe) 4-82 (ff[3:0]) 4-43 (ff4) 4-46 (ffl) 4-53 (flf) 4-56 (flsh) 4-51 (fm) 4-56 (fmt) 4-53 (gen) 4-75 , 4-79 (gen[3:0]) 4-85 (gensf) 4-85 (gpcntl0) 4-82 (gpio) 4-35 (gpio[1:0]) 4-83 (gpio[4:2]) 4-83 (gpreg0) 4-35 (hsc) 4-91 (ht) 4-8 (hth) 4-76 , 4-79 (hth[3:0]) 4-83 (hthba) 4-85 (hthsf) 4-85 (i/o) 4-9 , 4-37 , 4-45 (i_o) 4-39 (ia) 4-107 (iarb) 4-24 (iid) 4-40 , 4-69 (il) 4-13 (ilf) 4-42 (ilf1) 4-46 (intf) 4-49 (ip) 4-14 (irqd) 4-72 (irqm) 4-71 (iso) 4-88 (istat0) 4-48 (istat1) 4-51 (ldsc) 4-47 (ledc) 4-83 (loa) 4-43 (lock) 4-94 (low) 4-90 (lt) 4-8 (m/a) 4-73 (macntl) 4-81 (man) 4-68 (masr) 4-61 (mbox0) 4-52 (mbox1) 4-52 (mdpe) 4-40 , 4-69 (me) 4-82 (memory) 4-9 (mg) 4-14 (ml) 4-14 (mmrs) 4-100 (mmws) 4-101 (mo[4:0]) 4-33 (mpee) 4-59 (msg) 4-37 , 4-39 , 4-45 (nc) 4-6 (nip) 4-15 (olf) 4-42 (olf1) 4-46 (orf) 4-42 (orf1) 4-46 (par) 4-75 , 4-78 (pcicie) 4-54 (pen) 4-17 (pfen) 4-70 (pff) 4-70 (pmc) 4-15 (pmcsr) 4-16 (pmcsr_bse) 4-17 (pmec) 4-16 (pmes) 4-15 (pmjad1) 4-104 (pmjad2) 4-104 (pmjctl) 4-95 (pscpt) 4-82 (pst) 4-16 (pws[1:0]) 4-17 (qen) 4-88 (qsel) 4-89 (rbc) 4-105 (req) 4-37 , 4-39 (respid0) 4-86 (respid1) 4-86 (rid) 4-6 (rma) 4-5 (rof) 4-89 (rre) 4-30 (rsl) 4-74 , 4-77 (rst) 4-24 , 4-43 , 4-75 , 4-78 (rta) 4-5 (s16) 4-92 (sbc) 4-107 (sbcl) 4-38 (sbdl) 4-98 (sbms) 4-102 (sbr) 4-70 (sce) 4-89 (scf[2:0]) 4-29 (scid) 4-30 (sclk) 4-88 (scntl0) 4-20 (scntl1) 4-23 (scntl2) 4-26 (scntl3) 4-28 (scpts) 4-82 (scratcha) 4-65 (scratchb) 4-99 (scratchc?scratchr) 4-99 (scripts ram) 4-10 (sdid) 4-35 (sdp0) 4-43 (sdp0l) 4-45 (sdp1) 4-47 (sdu) 4-26 (se) 4-3 (sel) 4-37 , 4-39 , 4-74 , 4-77 (sel[3:0]) 4-84 (sem) 4-49 (sfbr) 4-36 (sfs) 4-101
index ix-3 (sge) 4-74 , 4-77 (si) 4-51 (sid) 4-11 (sien0) 4-73 (sien1) 4-75 (sigp) 4-49 , 4-54 (siom) 4-67 (sip) 4-50 (sir) 4-40 (sist0) 4-76 (sist1) 4-78 (slb) 4-89 (slpar) 4-79 (slphben) 4-27 (slpmd) 4-27 (slt) 4-87 (socl) 4-37 (sodl) 4-94 (som) 4-88 (soz) 4-87 (spl1) 4-47 (sre) 4-30 (srst) 4-48 (srtm) 4-59 (srun) 4-51 (ssaid) 4-87 (sse) 4-5 (ssi) 4-40 , 4-69 (ssid) 4-38 (ssm) 4-71 (sst) 4-25 (sstat0) 4-42 (sstat1) 4-43 (sstat2) 4-46 (start) 4-21 (std) 4-72 (stest0) 4-87 (stest1) 4-88 (stest2) 4-89 (stest3) 4-91 (stest4) 4-94 (stime0) 4-83 (stime1) 4-85 (sto) 4-75 , 4-79 (str) 4-91 (stw) 4-93 (swide) 4-81 (sxfer) 4-31 (szm) 4-90 (te) 4-91 (temp) 4-57 (teop) 4-55 (tp[2:0]) 4-31 (trg) 4-22 (ttm) 4-92 (typ) 4-81 (ua) 4-105 (udc) 4-74 , 4-78 (use) 4-28 (v) 4-56 (val) 4-38 (ver[2:0]) 4-16 (vid) 4-2 (vue0) 4-27 (vue1) 4-27 (watn) 4-22 (wie) 4-4 (woa) 4-43 (wrie) 4-57 (wsr) 4-28 (wss) 4-27 (zmode) 4-97 (zsd) 4-59 numerics 16-bit system (s16) 4-92 32-bit addressing 5-7 3-state 3-3 64-bit addressing in scripts 2-19 script selectors 4-99 table indirect indexing mode (64timod) 4-97 a a[6:0] 5-23 abort operation (abrt) 4-48 aborted (abrt) 4-40 , 4-69 absolute maximum stress ratings 6-2 ac characteristics 6-9 adder sum output (adder) 4-73 address/data bus 2-3 always wide scsi (aws) 4-90 arbitration in progress (aip) 4-43 mode bits 1 and 0 (arb[1:0]) 4-20 priority encoder test (art) 4-87 assert even scsi parity (force bad parity) (aesp) 4-24 satn/ on parity error (aap) 4-22 scsi ack/ signal (ack) 4-37 atn/ signal (atn) 4-37 bsy/ signal (bsy) 4-37 c_d/ signal (c_d) 4-37 data bus (adb) 4-23 i_o/ signal (i/o) 4-37 msg/ signal (msg) 4-37 req/ signal (req) 4-37 rst/ signal (rst) 4-24 sel/ signal (sel) 4-37 asynchronous scsi receive 2-31 send 2-29 auxiliary power source (aps) 4-16 b base address register one (bar1) 2-3 , 4-9 two (bar2) 4-10 zero - i/o (bar0) 4-9 bidirectional 3-3 signals 6-3 bios 2-3 bits used for parity control and generation 2-25 block move 2-9 instruction 5-6 bridge support extensions (bse) 4-17 burst disable (bdis) 4-59
ix-4 index burst (cont.) length (bl[1:0]) 4-66 length bit 2 (bl2) 4-61 opcode fetch enable (bof) 4-68 size selection 2-6 bus command and byte enables 3-5 fault (bf) 4-40 , 4-69 byte count 5-37 empty in dma fifo (fmt) 4-53 full in dma fifo (ffl) 4-53 offset counter (bo) 4-57 c cache line size 2-7 , 2-9 (cls) 4-7 enable (clse) 4-70 register 2-6 cache mode, see pci cache mode 2-9 call instruction 5-27 cap_id (cid) 4-15 capabilities pointer (cp) 4-13 carry test 5-30 chained block moves 2-44 scripts instruction 2-47 sodl register 2-46 swide register 2-46 wide scsi receive bit 2-46 wide scsi send bit 2-45 chained mode (chm) 4-26 change bus phases 2-17 chip control 0 (ccntl0) 4-95 control 1 (ccntl1) 4-97 revision level (v) 4-56 test five (ctest5) 4-60 test one (ctest1) 4-53 test six (ctest6) 4-62 test three (ctest3) 4-56 test two (ctest2) 4-54 test zero (ctest0) 4-53 type (typ) 4-81 chmov 2-44 class code (cc) 4-7 clear dma fifo 2-42 , 4-56 clear instruction 5-15 , 5-17 clear scsi fifo (csf) 4-92 clf 2-42 clk 3-4 clock 3-4 address incrementor (adck) 4-60 byte counter (bbck) 4-61 conversion factor (ccf[2:0]) 4-29 quadrupler 2-20 clse 2-6 , 2-7 cmp 2-39 compare data 5-31 phase 5-31 configuration read command 2-5 space 2-3 write command 2-5 configured as i/o (cio) 4-54 as memory (cm) 4-54 connected (con) 4-24 , 4-49 csf 2-42 ctest4 2-25 cumulative scsi byte count (csbc) 4-108 cycle frame 3-6 d d1_support (d1s) 4-16 d2_support (d2s) 4-16 dacs 2-19 data (data) 4-18 acknowledge status (dack) 4-55 compare mask 5-31 compare value 5-32 parity error reported (dpr) 4-6 paths 2-28 request status (dreq) 4-55 structure address (dsa) 4-47 transfer direction (ddir) 4-54 data read (drd) 4-82 data write (dwr) 4-82 data_scale (dscl) 4-17 data_select (dslt) 4-17 data-in 2-47 data-out 2-47 dcntl 2-6 , 2-39 decode of mad pins 3-14 default download mode 2-50 destination address 5-23 i/o memory enable (diom) 4-67 detected parity error (from slave) (dpe) 4-5 determining the data transfer rate 2-34 device id (did) 4-3 select 3-6 specific initialization (dsi) 4-16 devsel/ 3-6 timing (dt[1:0]) 4-5 dien 2-25 , 2-39 , 2-40 dip 2-38 , 2-41 , 2-42 , 2-43 direct 5-19 disable auto fifo clear (disfc) 4-96 dual address cycle (ddac) 4-97 halt on parity error or atn (target only) (dhp) 4-23 internal load and store (dils) 4-96 single initiator response (dsi) 4-92 disconnect 2-17 disconnect instruction 5-15 dma byte counter (dbc) 4-62 command (dcmd) 4-63 control (dcntl) 4-70 direction (ddir) 4-61 fifo 2-8 , 2-27 , 2-38 (df) 4-62 (dfifo) 4-57 byte offset counter, bits [9:8] (bo[9:8]) 4-62 empty (dfe) 4-39 size (dfs) 4-61 interrupt 2-39 , 2-40 , 2-42 enable (dien) 4-69
index ix-5 dma interrupt (cont.) pending (dip) 4-50 mode (dmode) 4-66 scripts pointer (dsp) 4-64 pointer save (dsps) 4-65 status (dstat) 4-39 dma next address (dnad) 4-64 address 64 (dnad64) 4-103 dmode 2-6 register 2-22 dsa relative 5-36 relative selector (drs) 4-102 dsps register 5-34 dstat 2-38 , 2-42 , 2-43 dual address cycles command 2-6 dynamic block move selector (dbms) 4-103 e enable 64-bit direct bmov (en64dbmv) 4-98 table indirect bmov (en64tibmv) 4-98 bus mastering (ebm) 4-4 i/o space (eis) 4-4 jump on nondata phase mismatches (enndj) 4-96 memory space (ems) 4-4 parity checking 2-24 checking (epc) 4-22 error response (eper) 4-3 phase mismatch jump (enpmj) 4-95 read line (erl) 4-67 multiple (ermp) 4-68 response to reselection (rre) 4-30 selection (sre) 4-30 wide scsi (ews) 4-29 enabling cache mode 2-10 encoded chip scsi id (enc) 4-30 destination scsi id (enc) 4-35 (enid) 4-38 scsi destination id 5-20 entry storage address (esa) 4-106 error reporting signals 3-7 even parity 2-24 expansion rom base address (erba) 4-12 address register 2-49 extend sreq/sack filtering (ext) 4-90 external clock 6-9 memory interface 2-49 configuration 2-49 slow memory 2-49 external memory interface multiple byte accesses 6-11 extra clock cycle of data setup (exc) 4-23 f fetch enable (fe) 4-82 pin mode (fm) 4-56 fifo byte control (fbl[2:0]) 4-60 byte control (fbl3) 4-59 flags (ff[3:0]) 4-43 flags, bit 4 (ff4) 4-46 first dword 5-6 , 5-14 , 5-22 , 5-26 , 5-36 flush dma fifo (flf) 4-56 flushing (flsh) 4-51 frame/ 3-6 frequency lock (lock) 4-94 full arbitration, selection/reselection 4-21 function complete 2-39 (cmp) 4-74 , 4-77 g general purpose (gpreg0) 4-35 i/o (gpio) 4-35 i/o pin 0 3-10 i/o pin 1 3-10 i/o pin 2 3-10 i/o pin 3 3-10 i/o pin 4 3-10 pin control zero (gpcntl0) 4-82 timer expired (gen) 4-75 , 4-79 timer period (gen[3:0]) 4-85 timer scale factor (gensf) 4-85 gnt/ 3-7 gpio enable, bits [1:0] (gpio[1:0]) 4-83 gpio enable, bits [4:2] (gpio[4:2]) 4-83 gpio0_ fetch/ 3-10 gpio1_ master/ 3-10 gpio2 3-10 gpio3 3-10 gpio4 3-10 grant 3-7 h halt scsi clock (hsc) 4-91 halting 2-42 handshake-to-handshake timer bus activity enable (hthba) 4-85 expired (hth) 4-76 , 4-79 period (hth[3:0]) 4-83 scale factor (hthsf) 4-85 hardware control of scsi activity led 2-19 hardware interrupts 2-37 header type (ht) 4-8 high impedance mode (szm) 4-90 high impedance mode (zmode) 4-97 i i/o 3-3 instructions 5-13 read command 2-5 space 2-2 , 2-3 write command 2-5
ix-6 index idsel 2-3 , 3-6 signal 2-5 illegal instruction detected (iid) 4-40 , 4-69 immediate arbitration (iarb) 4-24 data 5-23 indirect addressing 5-6 initialization device select 3-6 initiator mode 5-16 phase mismatch 4-76 ready 3-6 input 3-3 capacitance 6-2 instruction address (ia) 4-107 block move 5-6 prefetch unit flushing 2-21 type 5-36 block move 5-6 i/o instruction 5-14 memory move 5-33 read/write instruction 5-22 transfer control instruction 5-26 internal scripts ram 2-18 internal ram seealsoscripts ram 2-18 interrupt acknowledge command 2-4 handling 2-37 instruction 5-28 line (il) 4-13 on-the-fly 5-30 on-the-fly (intf) 4-49 on-the-fly instruction 5-28 output 6-10 pin (ip) 4-14 request 2-37 , 3-8 signals 3-8 status one (istat1) 4-51 status zero (istat0) 4-48 interrupts 2-39 fatal vs. nonfatal interrupts 2-39 halting 2-42 irq disable bit 2-39 masking 2-40 sample interrupt service routine 2-43 stacked interrupts 2-41 irdy/ 3-6 irq disable (irqd) 4-72 mode (irqm) 4-71 irq/ 2-37 , 3-8 pin 2-40 , 2-43 issuing cache commands 2-10 istat 2-37 , 2-43 j jtag boundary scan testing 2-23 jump address 5-32 call a relative address 5-29 call an absolute address 5-29 control (pmjctl) 4-95 if true/false 5-30 instruction 5-26 l last disconnect (ldsc) 4-47 latched scsi parity (sdp0l) 4-45 for sd[15:8] (spl1) 4-47 latency 2-9 timer (lt) 4-8 led_cntl (ledc) 4-83 load and store instructions 2-22 , 5-37 prefetch unit and store instructions 2-22 loopback enable 2-23 lost arbitration (loa) 4-43 lsi53c700 compatibility (com) 4-72 LSI53C875A new features 1-3 m mac/_testout 3-11 mad bus 2-49 bus programming 3-14 pins 2-49 mad[0] 3-15 mad[3:1] 3-14 mad[6:4] 3-14 mad[7:0] 3-12 , 3-14 mad[7] 3-14 mailbox one (mbox1) 4-52 mailbox zero (mbox0) 4-52 manual start mode (man) 4-68 mas0/ 3-11 mas1/ 3-11 masking 2-40 master control for set or reset pulses (masr) 4-61 data parity error (mdpe) 4-40 , 4-69 enable (me) 4-82 parity error enable (mpee) 4-59 max scsi synchronous offset (mo[4:0]) 4-33 max_lat (ml) 4-14 maximum stress ratings 6-2 mce/ 3-11 memory access control 3-11 (macntl) 4-81 address strobe 0 3-11 address strobe 1 3-11 address/data bus 3-12 chip enable 3-11 i/o address/dsa offset 5-37 move 2-9 move instructions 2-21 , 5-32 no flush option 2-21 move read selector (mmrs) 4-100 move write selector (mmws) 4-101 output enable 3-11 read 2-10 , 2-11 read caching 2-11 read command 2-5 read line 2-10 , 2-11
index ix-7 memory (cont.) read line command 2-6 read multiple 2-10 , 2-11 read multiple command 2-6 space 2-2 , 2-3 to memory 2-16 to memory moves 2-16 write 2-10 , 2-11 write and invalidate 2-10 write and invalidate command 2-8 write caching 2-11 write command 2-5 write enable 3-11 min_gnt (mg) 4-14 moe/ 3-11 move to/from sfbr cycles 5-24 multiple cache line transfers 2-8 mwe/ 3-11 n new capabilities (nc) 4-6 new features in the LSI53C875A 1-3 next_item_ptr (nip) 4-15 no connections 3-13 no download mode 2-51 no flush 5-33 store instruction only 5-36 not supported 4-8 , 4-10 o opcode 5-9 , 5-14 , 5-22 , 5-26 fetch burst capability 2-22 operating conditions 6-2 operator 5-22 p par 3-5 parallel rom interface 2-48 parallel rom support 2-49 parity 2-26 , 3-5 error 3-7 (par) 4-78 options 2-24 pci addressing 2-2 and external memory interface timing diagrams 6-11 bus commands and encoding types 2-4 bus commands and functions supported 2-3 cache line size register 2-8 cache mode 2-9 commands 2-3 configuration into enable (pcicie) 4-54 configuration register read 6-13 configuration registers 4-1 configuration space 2-2 functional description 2-2 i/o space 2-3 interface signals 3-4 master transaction 2-10 master transfer 2-10 memory space 2-3 performance 1-6 target disconnect 2-9 target retry 2-9 perr/ 3-7 phase mismatch handling in scripts 2-17 jump address 1 (pmjad1) 4-104 jump address 2 (pmjad2) 4-104 jump registers 4-103 physical dword address and data 3-5 pme clock (pmec) 4-16 enable (pen) 4-17 status (pst) 4-16 support (pmes) 4-15 pointer scripts (pscpt) 4-82 polling 2-37 power and ground signals 3-13 management 2-51 state (pws[1:0]) 4-17 state d0 2-52 state d1 2-52 state d2 2-53 state d3 2-53 prefetch enable (pfen) 4-70 flush 2-22 flush (pff) 4-70 scripts instructions 2-21 pull-ups, internal, conditions 3-3 r ram see also scripts ram 2-18 read line 2-10 function 2-7 modify-write cycles 5-23 multiple 2-7 multiple with read line enabled 2-7 write instructions 5-22 write system memory from scripts 5-34 read/write instructions 5-22 , 5-24 system memory from scripts 5-34 received master abort (from master) (rma) 4-5 target abort (from master) (rta) 4-5 register address 5-37 address - a[6:0] 5-23 registers 2-37 relative 5-19 relative addressing mode 5-18 , 5-29 remaining byte count (rbc) 4-105 req/ 3-7 request 3-7 reselect 2-17 during reselection 2-33 instruction 5-14 reselected (rsl) 4-74 , 4-77 reserved 4-3 , 4-4 , 4-5 , 4-6 , 4-10 , 4-13 , 4-16 , 4-17 , 4-22 , 4-30 , 4-35 , 4-38 , 4-40 , 4-51 , 4-69 , 4-75 , 4-79 , 4-85 , 4-88 , 4-94 , 4-96 , 4-97 , 4-99 , 4-103 , 4-108 command 2-5
ix-8 index reset 3-4 input 6-10 scsi offset (rof) 4-89 response id one (respid1) 4-86 response id zero (respid0) 4-86 return instruction 5-27 revision id (rid) 4-6 rom flash and memory interface signals 3-11 pin 2-49 rst/ 3-4 s sack 2-42 sack/ status (ack) 4-39 sacs 2-19 satn/ status (atn) 4-39 sbsy/ status (bsy) 4-39 sc_d/ status (c_d) 4-39 sclk 3-8 (sclk) 4-88 quadrupler enable (qen) 4-88 quadrupler select (qsel) 4-89 scntl0 2-25 scntl1 2-24 , 2-25 scntl3 2-36 scratch byte register (sbr) 4-70 register a (scratcha) 4-65 register b (scratchb) 4-99 registers c?r (scratchc?scratchr) 4-99 script fetch selector (sfs) 4-101 scripts (scpts) 4-82 instruction 2-46 interrupt instruction received (sir) 4-40 , 4-69 processor 2-17 internal ram for instruction storage 2-18 performance 2-17 ram 2-3 , 2-18 running (srun) 4-51 scsi atn condition - target mode (m/a) 4-73 bus control lines (sbcl) 4-38 bus data lines (sbdl) 4-98 bus interface 2-32 byte count (sbc) 4-107 c_d/ signal (c_d) 4-45 chip id (scid) 4-30 clock 3-8 control enable (sce) 4-89 control one (scntl1) 4-23 control three (scntl3) 4-28 control two (scntl2) 4-26 control zero (scntl0) 4-20 data high impedance (zsd) 4-59 destination id (sdid) 4-35 disconnect unexpected (sdu) 4-26 encoded destination id 5-20 fifo test read (str) 4-91 fifo test write (stw) 4-93 first byte received (sfbr) 4-36 functional description 2-16 gpio signals 3-10 gross error (sge) 4-74 , 4-77 i_o/ signal (i/o) 4-45 input data latch (sidl) 4-93 instructions block move 5-6 i/o 5-13 read/write 5-22 interface signals 3-8 interrupt enable one (sien1) 4-75 interrupt enable zero (sien0) 4-73 interrupt pending (sip) 4-50 interrupt status one (sist1) 4-78 interrupt status zero (sist0) 4-76 interrupts 2-42 isolation mode (iso) 4-88 longitudinal parity (slpar) 4-79 loopback mode 2-23 loopback mode (slb) 4-89 low level mode (low) 4-90 msg/ signal (msg) 4-45 output control latch (socl) 4-37 output data latch (sodl) 4-94 parity control 2-26 parity error (par) 4-75 performance 1-5 phase 5-11 , 5-28 phase mismatch - initiator mode 4-73 reset condition (rst) 4-75 rst/ received (rst) 4-78 rst/ signal (rst) 4-43 scripts operation 5-2 sample instruction 5-3 sdp0/ parity signal (sdp0) 4-43 sdp1 signal (sdp1) 4-47 selected as id (ssaid) 4-87 selector id (ssid) 4-38 serial eeprom access 2-50 signals 3-9 status one (sstat1) 4-43 status two (sstat2) 4-46 status zero (sstat0) 4-42 synchronous offset maximum (som) 4-88 synchronous offset zero (soz) 4-87 synchronous transfer period (tp[2:0]) 4-31 termination 2-32 test four (stest4) 4-94 test one (stest1) 4-88 test three (stest3) 4-91 test two (stest2) 4-89 test zero (stest0) 4-87 timer one (stime1) 4-85 timer zero (stime0) 4-83 tolerant technology 1-4 transfer (sxfer) 4-31 true end of process (teop) 4-55 ultra scsi 2-20 valid (val) 4-38 wide residue (swide) 4-81 scsi-2 fast transfers 10.0 mbytes (8-bit transfers) 40 mhz clock 6-56 20.0 mbytes (16-bit transfers) 40 mhz clock 6-56 sctrl signals 3-9 sd[15:0] 3-9 second dword 5-13 , 5-21 , 5-23 , 5-32 , 5-34 , 5-37
index ix-9 sel 2-39 select 2-17 instruction 5-16 with atn/ 5-20 with satn/ on a start sequence (watn) 4-22 selected (sel) 4-74 , 4-77 selection or reselection time-out (sto) 4-75 , 4-79 selection response logic test (slt) 4-87 selection time-out (sel[3:0]) 4-84 semaphore (sem) 4-49 serial eeprom interface 2-50 serr/ 3-7 serr/ enable (se) 4-3 set instruction 5-15 , 5-17 set/clear carry 5-20 sack/ 5-21 shadow register test mode (srtm) 4-59 si_o/ status (i_o) 4-39 sid 2-51 sidl least significant byte full (ilf) 4-42 most significant byte full (ilf1) 4-46 sien0 2-39 sien1 2-39 signal process (sigp) 4-49 , 4-54 signaled system error (sse) 4-5 simple arbitration 4-20 single address cycles 2-19 ended scsi signals 6-6 step interrupt (ssi) 4-40 , 4-69 step mode (ssm) 4-71 sip 2-38 , 2-41 , 2-42 sist0 2-25 , 2-38 , 2-41 , 2-43 sist1 2-38 , 2-41 , 2-43 slow rom pin 3-15 slpar high byte enable (slphben) 4-27 slpar mode (slpmd) 4-27 smsg/ status (msg) 4-39 sodl least significant byte full (olf) 4-42 most significant byte full (olf1) 4-46 register 2-45 , 2-46 , 2-47 sodr least significant byte full (orf) 4-42 most significant byte full (orf1) 4-46 software reset (srst) 4-48 source i/o memory enable (siom) 4-67 special cycle command 2-4 sreq 2-42 sreq/ status (req) 4-39 ssel/ status (sel) 4-39 sstat0 2-25 sstat1 2-25 stacked interrupts 2-41 start address 5-13 , 5-21 dma operation (std) 4-72 scsi transfer (sst) 4-25 sequence (start) 4-21 static block move selector (sbms) 4-102 stest2 register 2-23 stop command 2-9 stop signal 3-6 stop/ signal 3-6 store 2-22 stress ratings 6-2 subsystem id 2-51 subsystem id (sid) 4-11 subsystem vendor id 2-51 subsystem vendor id (svid) 4-10 svid 2-51 swide register 2-46 , 2-47 sxfer 2-36 sync_irqd (si) 4-51 synchronous data transfer rates 2-34 operation 2-34 scsi receive 2-31 scsi send 2-30 synchronous clock conversion factor (scf[2:0]) 4-29 system signals 3-4 t table indirect 5-19 mode 5-18 table relative 5-20 target mode 5-9 , 5-14 satn/ active (m/a) 4-76 mode (trg) 4-22 ready 3-6 timing 6-13 tck 3-12 tdi 3-12 tdo 3-12 temp register 5-35 temporary (temp) 4-57 test interface signals 3-12 test_hsc/ 3-12 test_rst/ 3-12 third dword 5-35 timer test mode (ttm) 4-92 tms 3-12 tolerant 1-4 , 6-5 enable (te) 4-91 technology 1-4 benefits 1-4 electrical characteristics 6-5 totem pole output 3-3 transfer control 2-22 control instructions 5-25 and scripts instruction prefetching 2-22 counter 5-12 , 5-33 information 2-17 rate synchronous 2-34 trdy/ 2-9 , 3-6 trst/ 3-12 u ultra scsi 1-3 benefits 1-3 clock conversion factor bits 4-29 designing an ultra scsi system 2-20 enable (use) 4-28
ix-10 index ultra scsi (cont.) single-ended transfers 20.0 mbytes (16-bit transfers) quadrupled 40 mhz clock 6-56 20.0 mbytes (8-bit transfers) 40 mhz clock 6-56 synchronous data transfers 2-36 unexpected disconnect (udc) 4-74 , 4-78 updated address (ua) 4-105 upper register address line (a7) 5-23 use data8/sfbr 5-22 v vdd 3-13 -a 3-13 -core 3-13 vendor id (vid) 4-2 unique enhancement, bit 1 (vue1) 4-27 unique enhancements, bit 0 (vue0) 4-27 version (ver[2:0]) 4-16 vss 3-13 -a 3-13 -core 3-13 w wait disconnect instruction 5-17 for a disconnect 2-17 for valid phase 5-31 reselect instruction 5-17 select instruction 5-15 wide scsi chained block moves 2-44 receive (wsr) 4-28 receive bit 2-46 send (wss) 4-27 send bit 2-45 won arbitration (woa) 4-43 write read instructions 5-22 read system memory from scripts 5-34 write and invalidate enable (wie) 4-4 enable (wrie) 4-57 wsr bit 2-46 wss flag 2-45
customer feedback we would appreciate your feedback on this document. please copy the following page, add your comments, and fax it to us at the number shown. if appropriate, please also fax copies of any marked-up pages from this document. important: please include your name, phone number, fax number, and company address so that we may contact you directly for clarification or additional information. thank you for your help in improving the quality of our documents.
customer feedback reader?s comments fax your comments to: lsi logic corporation technical publications m/s e-198 fax: 408.433.4333 please tell us how you rate this document: LSI53C875A pci to ultra scsi controller technical manual. place a check mark in the appropriate blank for each category. whatcouldwedotoimprovethisdocument? if you found errors in this document, please specify the error and page number. if appropriate, please fax a marked-up copy of the page(s). please complete the information below so that we may contact you directly for clarification or additional information. excellent good average fair poor completeness of information ____ ____ ____ ____ ____ clarity of information ____ ____ ____ ____ ____ ease of finding information ____ ____ ____ ____ ____ technical content ____ ____ ____ ____ ____ usefulness of examples and illustrations ____ ____ ____ ____ ____ overall manual ____ ____ ____ ____ ____ name date telephone title company name street city, state, zip department mail stop fax
u.s. distributors by state a. e. avnet electronics http://www.hh.avnet.com b. m. bell microproducts, inc. (for hab?s) http://www.bellmicro.com i. e. insight electronics http://www.insight-electronics.com w. e. wyle electronics http://www.wyle.com alabama daphne i. e. tel: 334.626.6190 huntsville a. e. tel: 256.837.8700 b. m. tel: 256.705.3559 i. e. tel: 256.830.1222 w. e. tel: 800.964.9953 alaska a. e. tel: 800.332.8638 arizona phoenix a. e. tel: 480.736.7000 b. m. tel: 602.267.9551 w. e. tel: 800.528.4040 te m p e i. e. tel: 480.829.1800 tucson a. e. tel: 520.742.0515 arkansas w. e. tel: 972.235.9953 california agoura hills b. m. tel: 818.865.0266 granite bay b. m. tel: 916.523.7047 irvine a. e. tel: 949.789.4100 b. m. tel: 949.470.2900 i. e. tel: 949.727.3291 w. e. tel: 800.626.9953 los angeles a. e. tel: 818.594.0404 w. e. tel: 800.288.9953 sacramento a. e. tel: 916.632.4500 w. e. tel: 800.627.9953 san diego a. e. tel: 858.385.7500 b. m. tel: 858.597.3010 i. e. tel: 800.677.6011 w. e. tel: 800.829.9953 san jose a. e. tel: 408.435.3500 b. m. tel: 408.436.0881 i. e. tel: 408.952.7000 santa clara w. e. tel: 800.866.9953 woodland hills a. e. tel: 818.594.0404 westlake village i. e. tel: 818.707.2101 colorado denver a. e. tel: 303.790.1662 b. m. tel: 303.846.3065 w. e. tel: 800.933.9953 englewood i. e. tel: 303.649.1800 idaho springs b. m. tel: 303.567.0703 connecticut cheshire a. e. tel: 203.271.5700 i. e. tel: 203.272.5843 wallingford w. e. tel: 800.605.9953 delaware north/south a. e. tel: 800.526.4812 tel: 800.638.5988 b. m. tel: 302.328.8968 w. e. tel: 856.439.9110 florida altamonte springs b. m. tel: 407.682.1199 i. e. tel: 407.834.6310 boca raton i. e. tel: 561.997.2540 bonita springs b. m. tel: 941.498.6011 clearwater i. e. tel: 727.524.8850 fort lauderdale a. e. tel: 954.484.5482 w. e. tel: 800.568.9953 miami b. m. tel: 305.477.6406 orlando a. e. tel: 407.657.3300 w. e. tel: 407.740.7450 ta m p a w. e. tel: 800.395.9953 st. petersburg a. e. tel: 727.507.5000 georgia atlanta a. e. tel: 770.623.4400 b. m. tel: 770.980.4922 w. e. tel: 800.876.9953 duluth i. e. tel: 678.584.0812 hawaii a. e. tel: 800.851.2282 idaho a. e. tel: 801.365.3800 w. e. tel: 801.974.9953 illinois north/south a. e. tel: 847.797.7300 tel: 314.291.5350 chicago b. m. tel: 847.413.8530 w. e. tel: 800.853.9953 schaumburg i. e. tel: 847.885.9700 indiana fort wayne i. e. tel: 219.436.4250 w. e. tel: 888.358.9953 indianapolis a. e. tel: 317.575.3500 iowa w. e. tel: 612.853.2280 cedar rapids a. e. tel: 319.393.0033 kansas w. e. tel: 303.457.9953 kansas city a. e. tel: 913.663.7900 lenexa i. e. tel: 913.492.0408 kentucky w. e. tel: 937.436.9953 central/northern/ western a. e. tel: 800.984.9503 tel: 800.767.0329 tel: 800.829.0146 louisiana w. e. tel: 713.854.9953 north/south a. e. tel: 800.231.0253 tel: 800.231.5775 maine a. e. tel: 800.272.9255 w. e. tel: 781.271.9953 maryland baltimore a. e. tel: 410.720.3400 w. e. tel: 800.863.9953 columbia b. m. tel: 800.673.7461 i. e. tel: 410.381.3131 massachusetts boston a. e. tel: 978.532.9808 w. e. tel: 800.444.9953 burlington i. e. tel: 781.270.9400 marlborough b. m. tel: 800.673.7459 woburn b. m. tel: 800.552.4305 michigan brighton i. e. tel: 810.229.7710 detroit a. e. tel: 734.416.5800 w. e. tel: 888.318.9953 clarkston b. m. tel: 877.922.9363 minnesota champlin b. m. tel: 800.557.2566 eden prairie b. m. tel: 800.255.1469 minneapolis a. e. tel: 612.346.3000 w. e. tel: 800.860.9953 st. louis park i. e. tel: 612.525.9999 mississippi a. e. tel: 800.633.2918 w. e. tel: 256.830.1119 missouri w. e. tel: 630.620.0969 st. louis a. e. tel: 314.291.5350 i. e. tel: 314.872.2182 montana a. e. tel: 800.526.1741 w. e. tel: 801.974.9953 nebraska a. e. tel: 800.332.4375 w. e. tel: 303.457.9953 nevada las vegas a. e. tel: 800.528.8471 w. e. tel: 702.765.7117 new hampshire a. e. tel: 800.272.9255 w. e. tel: 781.271.9953 new jersey north/south a. e. tel: 201.515.1641 tel: 609.222.6400 mt. laurel i. e. tel: 856.222.9566 pine brook b. m. tel: 973.244.9668 w. e. tel: 800.862.9953 parsippany i. e. tel: 973.299.4425 wayne w. e. tel: 973.237.9010 new mexico w. e. tel: 480.804.7000 albuquerque a. e. tel: 505.293.5119
u.s. distributors by state (continued) new york hauppauge i. e. tel: 516.761.0960 long island a. e. tel: 516.434.7400 w. e. tel: 800.861.9953 rochester a. e. tel: 716.475.9130 i. e. tel: 716.242.7790 w. e. tel: 800.319.9953 smithtown b. m. tel: 800.543.2008 syracuse a. e. tel: 315.449.4927 north carolina raleigh a. e. tel: 919.859.9159 i. e. tel: 919.873.9922 w. e. tel: 800.560.9953 north dakota a. e. tel: 800.829.0116 w. e. tel: 612.853.2280 ohio cleveland a. e. tel: 216.498.1100 w. e. tel: 800.763.9953 dayton a. e. tel: 614.888.3313 i. e. tel: 937.253.7501 w. e. tel: 800.575.9953 strongsville b. m. tel: 440.238.0404 valley view i. e. tel: 216.520.4333 oklahoma w. e. tel: 972.235.9953 tu l s a a. e. tel: 918.459.6000 i. e. tel: 918.665.4664 oregon beaverton b. m. tel: 503.524.1075 i. e. tel: 503.644.3300 portland a. e. tel: 503.526.6200 w. e. tel: 800.879.9953 pennsylvania mercer i. e. tel: 412.662.2707 philadelphia a. e. tel: 800.526.4812 b. m. tel: 877.351.2355 w. e. tel: 800.871.9953 pittsburgh a. e. tel: 412.281.4150 w. e. tel: 440.248.9996 rhode island a. e. 800.272.9255 w. e. tel: 781.271.9953 south carolina a. e. tel: 919.872.0712 w. e. tel: 919.469.1502 south dakota a. e. tel: 800.829.0116 w. e. tel: 612.853.2280 tennessee w. e. tel: 256.830.1119 east/west a. e. tel: 800.241.8182 tel: 800.633.2918 texas arlington b. m. tel: 817.417.5993 austin a. e. tel: 512.219.3700 b. m. tel: 512.258.0725 i. e. tel: 512.719.3090 w. e. tel: 800.365.9953 dallas a. e. tel: 214.553.4300 b. m. tel: 972.783.4191 w. e. tel: 800.955.9953 el paso a. e. tel: 800.526.9238 houston a. e. tel: 713.781.6100 b. m. tel: 713.917.0663 w. e. tel: 800.888.9953 richardson i. e. tel: 972.783.0800 rio grande valley a. e. tel: 210.412.2047 stafford i. e. tel: 281.277.8200 utah centerville b. m. tel: 801.295.3900 murray i. e. tel: 801.288.9001 salt lake city a. e. tel: 801.365.3800 w. e. tel: 800.477.9953 vermont a. e. tel: 800.272.9255 w. e. tel: 716.334.5970 virginia a. e. tel: 800.638.5988 w. e. tel: 301.604.8488 haymarket b. m. tel: 703.754.3399 springfield b. m. tel: 703.644.9045 washington kirkland i. e. tel: 425.820.8100 maple valley b. m. tel: 206.223.0080 seattle a. e. tel: 425.882.7000 w. e. tel: 800.248.9953 west virginia a. e. tel: 800.638.5988 wisconsin milwaukee a. e. tel: 414.513.1500 w. e. tel: 800.867.9953 wauwatosa i. e. tel: 414.258.5338 wyoming a. e. tel: 800.332.9326 w. e. tel: 801.974.9953
direct sales representatives by state (component and hab) e. a. earle associates e. l. electrodyne - ut grp group 2000 i. s. infinity sales, inc. ion ion associates, inc. r. a. rathsburg associ- ates, inc. sgy synergy associates, inc. arizona te m p e e. a. tel: 480.921.3305 california calabasas i. s. tel: 818.880.6480 irvine i. s. tel: 714.833.0300 san diego e. a. tel: 619.278.5441 illinois elmhurst r. a. tel: 630.516.8400 indiana cicero r. a. tel: 317.984.8608 ligonier r. a. tel: 219.894.3184 plainfield r. a. tel: 317.838.0360 massachusetts burlington sgy tel: 781.238.0870 michigan byron center r. a. tel: 616.554.1460 good rich r. a. tel: 810.636.6060 novi r. a. tel: 810.615.4000 north carolina cary grp tel: 919.481.1530 ohio columbus r. a. tel: 614.457.2242 dayton r. a. tel: 513.291.4001 independence r. a. tel: 216.447.8825 pennsylvania somerset r. a. tel: 814.445.6976 texas austin ion tel: 512.794.9006 arlington ion tel: 817.695.8000 houston ion tel: 281.376.2000 utah salt lake city e. l. tel: 801.264.8050 wisconsin muskego r. a. tel: 414.679.8250 saukville r. a. tel: 414.268.1152
sales offices and design resource centers lsi logic corporation corporate headquarters 1551 mccarthy blvd milpitas ca 95035 tel: 408.433.8000 fax: 408.433.8989 north america california irvine 18301 von karman ave suite 900 irvine, ca 92612 ? tel: 949.809.4600 fax: 949.809.4444 pleasanton design center 5050 hopyard road, 3rd floor suite 300 pleasanton, ca 94588 tel: 925.730.8800 fax: 925.730.8700 san diego 7585 ronson road suite 100 san diego, ca 92111 tel: 858.467.6981 fax: 858.496.0548 silicon valley 1551 mccarthy blvd sales office m/s c-500 milpitas, ca 95035 ? tel: 408.433.8000 fax: 408.954.3353 design center m/s c-410 tel: 408.433.8000 fax: 408.433.7695 wireless design center 11452 el camino real suite 210 san diego, ca 92130 tel: 858.350.5560 fax: 858.350.0171 colorado boulder 4940 pearl east circle suite 201 boulder, co 80301 ? tel: 303.447.3800 fax: 303.541.0641 colorado springs 4420 arrowswest drive colorado springs, co 80907 tel: 719.533.7000 fax: 719.533.7020 fort collins 2001 danfield court fort collins, co 80525 tel: 970.223.5100 fax: 970.206.5549 florida boca raton 2255 glades road suite 324a boca raton, fl 33431 tel: 561.989.3236 fax: 561.989.3237 georgia alpharetta 2475 north winds parkway suite 200 alpharetta, ga 30004 tel: 770.753.6146 fax: 770.753.6147 illinois oakbrook terrace two mid american plaza suite 800 oakbrook terrace, il 60181 tel: 630.954.2234 fax: 630.954.2235 kentucky bowling green 1262 chestnut street bowling green, ky 42101 tel: 270.793.0010 fax: 270.793.0040 maryland bethesda 6903 rockledge drive suite 230 bethesda, md 20817 tel: 301.897.5800 fax: 301.897.8389 massachusetts waltham 200 west street waltham, ma 02451 ? tel: 781.890.0180 fax: 781.890.6158 burlington - mint technology 77 south bedford street burlington, ma 01803 tel: 781.685.3800 fax: 781.685.3801 minnesota minneapolis 8300 norman center drive suite 730 minneapolis, mn 55437 ? tel: 612.921.8300 fax: 612.921.8399 new jersey red bank 125 half mile road suite 200 red bank, nj 07701 tel: 732.933.2656 fax: 732.933.2643 cherry hill - mint technology 215 longstone drive cherry hill, nj 08003 tel: 856.489.5530 fax: 856.489.5531 new york fairport 550 willowbrook office park fairport, ny 14450 tel: 716.218.0020 fax: 716.218.9010 north carolina raleigh phase ii 4601 six forks road suite 528 raleigh, nc 27609 tel: 919.785.4520 fax: 919.783.8909 oregon beaverton 15455 nw greenbrier parkway suite 235 beaverton, or 97006 tel: 503.645.0589 fax: 503.645.6612 texas austin 9020 capital of tx highway north building 1 suite 150 austin, tx 78759 tel: 512.388.7294 fax: 512.388.4171 plano 500 north central expressway suite 440 plano, tx 75074 ? tel: 972.244.5000 fax: 972.244.5001 houston 20405 state highway 249 suite 450 houston, tx 77070 tel: 281.379.7800 fax: 281.379.7818 canada ontario ottawa 260 hearst way suite 400 kanata, on k2l 3h1 ? tel: 613.592.1263 fax: 613.592.3253 international france paris lsi logic s.a. immeuble europa 53 bis avenue de l'europe b.p. 139 78148 velizy-villacoublay cedex, paris ? tel: 33.1.34.63.13.13 fax: 33.1.34.63.13.19 germany munich lsi logic gmbh orleansstrasse 4 81669 munich ? tel: 49.89.4.58.33.0 fax: 49.89.4.58.33.108 stuttgart mittlerer pfad 4 d-70499 stuttgart ? tel: 49.711.13.96.90 fax: 49.711.86.61.428 italy milan lsi logic s.p.a. centro direzionale colleoni palazzo orione ingresso 1 20041 agrate brianza, milano ? tel: 39.039.687371 fax: 39.039.6057867 japan tokyo lsi logic k.k. rivage-shinagawa bldg. 14f 4-1-8 kounan minato-ku, tokyo 108-0075 ? tel: 81.3.5463.7821 fax: 81.3.5463.7820 osaka crystal tower 14f 1-2-27 shiromi chuo-ku, osaka 540-6014 ? tel: 81.6.947.5281 fax: 81.6.947.5287
sales offices and design resource centers (continued) korea seoul lsi logic corporation of korea ltd 10th fl., haesung 1 bldg. 942, daechi-dong, kangnam-ku, seoul, 135-283 tel: 82.2.528.3400 fax: 82.2.528.2250 the netherlands eindhoven lsi logic europe ltd world trade center eindhoven building ?rijder? bogert 26 5612 lz eindhoven tel: 31.40.265.3580 fax: 31.40.296.2109 singapore singapore lsi logic pte ltd 7 temasek boulevard #28-02 suntec tower one singapore 038987 tel: 65.334.9061 fax: 65.334.4749 sweden stockholm lsi logic ab finlandsgatan 14 164 74 kista ? tel: 46.8.444.15.00 fax: 46.8.750.66.47 taiwan ta i p e i lsi logic asia, inc. taiwan branch 10/f 156 min sheng e. road section 3 taipei, taiwan r.o.c. tel: 886.2.2718.7828 fax: 886.2.2718.8869 united kingdom bracknell lsi logic europe ltd greenwood house london road bracknell, berkshire rg12 2ub ? tel: 44.1344.426544 fax: 44.1344.481039 ? sales offices with design resource centers
international distributors australia new south wales reptechnic pty ltd 3/36 bydown street neutral bay, nsw 2089 ? tel: 612.9953.9844 fax: 612.9953.9683 belgium acal nv/sa lozenberg 4 1932 zaventem tel: 32.2.7205983 fax: 32.2.7251014 china beijing lsi logic international services inc. beijing representative office room 708 canway building 66 nan li shi lu xicheng district beijing 100045, china tel: 86.10.6804.2534 to 38 fax: 86.10.6804.2521 france rungis cedex azzurri technology france 22 rue saarinen sillic 274 94578 rungis cedex tel: 33.1.41806310 fax: 33.1.41730340 germany haar ebv elektronik hans-pinsel str. 4 d-85540 haar tel: 49.89.4600980 fax: 49.89.46009840 munich avnet emg gmbh stahlgruberring 12 81829 munich tel: 49.89.45110102 fax: 49.89.42.27.75 wuennenberg-haaren peacock ag graf-zepplin-str 14 d-33181 wuennenberg-haaren tel: 49.2957.79.1692 fax: 49.2957.79.9341 hong kong hong kong avt industrial ltd unit 608 tower 1 cheung sha wan plaza 833 cheung sha wan road kowloon, hong kong tel: 852.2428.0008 fax: 852.2401.2105 serial system (hk) ltd 2301 nanyang plaza 57 hung to road, kwun tong kowloon, hong kong tel: 852.2995.7538 fax: 852.2950.0386 india bangalore spike technologies india private ltd 951, vijayalakshmi complex, 2nd floor, 24th main, j p nagar ii phase, bangalore, india 560078 ? tel: 91.80.664.5530 fax: 91.80.664.9748 israel te l av i v eastronics ltd 11 rozanis street p.o. box 39300 tel aviv 61392 tel: 972.3.6458777 fax: 972.3.6458666 japan tokyo daito electron sogo kojimachi no.3 bldg 1-6 kojimachi chiyoda-ku, tokyo 102-8730 tel: 81.3.3264.0326 fax: 81.3.3261.3984 global electronics corporation nichibei time24 bldg. 35 tansu-cho shinjuku-ku, tokyo 162-0833 tel: 81.3.3260.1411 fax: 81.3.3260.7100 technical center tel: 81.471.43.8200 marubeni solutions 1-26-20 higashi shibuya-ku, tokyo 150-0001 tel: 81.3.5778.8662 fax: 81.3.5778.8669 shinki electronics myuru daikanyama 3f 3-7-3 ebisu minami shibuya-ku, tokyo 150-0022 tel: 81.3.3760.3110 fax: 81.3.3760.3101 yokohama-city innotech 2-15-10 shin yokohama kohoku-ku yokohama-city, 222-8580 tel: 81.45.474.9037 fax: 81.45.474.9065 macnica corporation hakusan high-tech park 1-22-2 hadusan, midori-ku, yokohama-city, 226-8505 tel: 81.45.939.6140 fax: 81.45.939.6141 the netherlands eindhoven acal nederland b.v. beatrix de rijkweg 8 5657 eg eindhoven tel: 31.40.2.502602 fax: 31.40.2.510255 switzerland brugg lsi logic sulzer ag mattenstrasse 6a ch 2555 brugg tel: 41.32.3743232 fax: 41.32.3743233 taiwan ta i p e i avnet-mercuries corporation, ltd 14f, no. 145, sec. 2, chien kuo n. road taipei, taiwan, r.o.c. tel: 886.2.2516.7303 fax: 886.2.2505.7391 lumax international corporation, ltd 7th fl., 52, sec. 3 nan-kang road taipei, taiwan, r.o.c. tel: 886.2.2788.3656 fax: 886.2.2788.3568 prospect technology corporation, ltd 4fl., no. 34, chu luen street taipei, taiwan, r.o.c. tel: 886.2.2721.9533 fax: 886.2.2773.3756 wintech microeletronics co., ltd 7f., no. 34, sec. 3, pateh road taipei, taiwan, r.o.c. tel: 886.2.2579.5858 fax: 886.2.2570.3123 united kingdom maidenhead azzurri technology ltd 16 grove park business estate waltham road white waltham maidenhead, berkshire sl6 3lw tel: 44.1628.826826 fax: 44.1628.829730 milton keynes ingram micro (uk) ltd garamonde drive wymbush milton keynes buckinghamshire mk8 8df tel: 44.1908.260422 swindon ebv elektronik 12 interface business park bincknoll lane wootton bassett, swindon, wiltshire sn4 8sy tel: 44.1793.849933 fax: 44.1793.859555 ? sales offices with design resource centers

▲Up To Search▲

Price & Availability of LSI53C875A

	To Download LSI53C875A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .